WBZ350_SL3 BTZBSYS registers The 7 registers of BTZBSYS (BT ZB Subsystem), from 0x41014000, with their reset value and every field. The WBZ350_SL3 has 2134 registers in 59 peripherals, one page each.
BTZBSYS BT ZB Subsystem SUBSYS_CNTRL_REG0SUBSYS_CNTRL_REG0
Address 0x41014000
Reset 0x00000000
Access read/write
Size 32-bit 20 fields
Field Bits What it does ant_div_sel_ovrd_val 30:29 ant_div_sel_ovrd_val disable_pclk_bt 28 disable_pclk_bt disable_pclk_zb_mac 27 disable_pclk_zb_mac disable_pclk_arb 26 disable_pclk_arb subsys_dbg_bus_sel 25 subsys_dbg_bus_sel aclb_pwr_rst_n 24 aclb_pwr_rst_n aclb_soft_rst_n 23 aclb_soft_rst_n subsys_dbg_bus_sel_top 22 subsys_dbg_bus_sel_top bt_en_main_clk 20 bt_en_main_clk bt_reset_by_fw 19 bt_reset_by_fw bt_hw_rc_re_cal 18 bt_hw_rc_re_cal bt_sfr_wakeup_bit 17 bt_sfr_wakeup_bit bt_pdc_ov 16 bt_pdc_ov ant_div_sel_2_iom_en 6 ant_div_sel_2_iom_en ant_div_sel_1_iom_en 5 ant_div_sel_1_iom_en zb_en_main_clk 4 zb_en_main_clk zb_reset_by_fw 3 zb_reset_by_fw zb_soft_reset_in 1 zb_soft_reset_in zb_slp_ctrl 0 zb_slp_ctrl ant_div_sel_ovrd_en 31 ant_div_sel_ovrd_en
SUBSYS_CNTRL_REG1SUBSYS_CNTRL_REG1
Address 0x41014004
Reset 0x00001800
Access read/write
Size 32-bit 21 fields
Field Bits What it does die_clk_sel 30 die_clk_sel pll_lock_flops_rstn_ovrd_val 29 pll_lock_flops_rstn_ovrd_val pll_lock_flops_rstn_ovrd_en 28 pll_lock_flops_rstn_ovrd_en xtal_lock_cnt_rstn_ovrd_val 27 xtal_lock_cnt_rstn_ovrd_val xtal_lock_cnt_rstn_ovrd_en 26 xtal_lock_cnt_rstn_ovrd_en clk_lp_req 23 clk_lp_req invert_btadc_clk 22 invert_btadc_clk zb_bt_bar_ovrd_val 21 zb_bt_bar_ovrd_val zb_bt_bar_ovrd_en 20 zb_bt_bar_ovrd_en lna_on_iom_en 19 lna_on_iom_en pa_on_iom_en 18 pa_on_iom_en tr_sw_n_iom_en 17 tr_sw_n_iom_en tr_sw_iom_en 16 tr_sw_iom_en subsys_xtal_ready_delay 15:12 subsys_xtal_ready_delay subsys_dbg_bus_en 11 subsys_dbg_bus_en disable_one_sec_counter 10 disable_one_sec_counter ssubsys_clk_div_sel 6 subsys_clk_div_sel subsys_clk_src_sel 5:4 subsys_clk_src_sel subsys_dbg_bus_sel 3:2 subsys_dbg_bus_sel subsys_dbg_bus_sel_top 1:0 subsys_dbg_bus_sel_top disable_adc_clk_gating 31 disable_adc_clk_gating
SUBSYS_CNTRL_REG2SUBSYS_CNTRL_REG2
Address 0x41014008
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does crossbar_data_line_sel_5 22:20 crossbar_data_line_sel_5 crossbar_data_line_sel_4 18:16 crossbar_data_line_sel_4 crossbar_data_line_sel_3 14:12 crossbar_data_line_sel_3 crossbar_data_line_sel_2 10:8 crossbar_data_line_sel_2 crossbar_data_line_sel_1 6:4 crossbar_data_line_sel_1 crossbar_data_line_sel_0 2:0 crossbar_data_line_sel_0 crossbar_data_invert 31:26 crossbar_data_invert
SUBSYS_CNTRL_REG3SUBSYS_CNTRL_REG3
Address 0x4101400C
Reset 0x00000240
Access read/write
Size 32-bit 9 fields
Field Bits What it does pll_lock_fifo_empty_rst_en 13 pll_lock_fifo_empty_rst_en pll_lock_fifo_clk_src_sel 12 pll_lock_fifo_clk_src_sel pll_lock_fifo_empty_soft_reset 11 pll_lock_fifo_empty_soft_reset pll_auto_relock_en 10 pll_auto_relock_en pll_lock_fifo_en 9 pll_lock_fifo_en disable_pclk_zb_mdm 8 disable_pclk_zb_mdm disable_pclk_dfe 7 disable_pclk_dfe subsys_pll_ready_delay 6:1 subsys_pll_ready_delay le_2m_fpga_v1c0_mode 0 le_2m_fpga_v1c0_mode
SUBSYS_STATUS_REG0SUBSYS_STATUS_REG0
Address 0x41014020
Reset 0x00000000
Access read only
Size 32-bit 5 fields
Field Bits What it does bt_rf_idle 17 bt_rf_idle bt_low_power_mode 16 bt_low_power_mode radio_idle_zb 2 radio_idle_zb zb_deep_sleep_mode 1 zb_deep_sleep_mode zb_sleep_mode 0 zb_sleep_mode
SUBSYS_STATUS_REG1SUBSYS_STATUS_REG1
Address 0x41014024
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does pllc_ready_cnt_expire_raw 8 pllc_ready_cnt_expire_raw pll_lock_fifo_empty 7 XTAL_ready clk_mux_sel 6:5 clk_mux_sel0 clk_lp_ready 4 clk_lp_ready PLL_locked 3 PLL_locked XTAL_ready 2 XTAL_ready pll_lock_out 1 pll_lock_out xtal_ready_out 0 xtal_ready_out
SUBSYS_STATUS_REG2SUBSYS_STATUS_REG2
Address 0x41014028
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does PART_NUM 15:8 PART_NUM VERSION_NUM 7:0 VERSION_NUM
BETA