WBZ451H QSPI registers

The 14 registers of QSPI (Quad SPI interface), from 0x42000000, with their reset value and every field. The WBZ451H has 1990 registers in 54 peripherals, one page each.

QSPI Quad SPI interface

CTRLAControl A

Address
0x42000000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
ENABLE1Enable
SWRST0Software Reset

CTRLBControl B

Address
0x42000004
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBCT23:16Delay Between Consecutive Transfers
DATALEN11:8Data Length
  • 0 8-bits transfer
  • 1 9 bits transfer
  • 2 10-bits transfer
  • 3 11-bits transfer
  • 4 12-bits transfer
  • 5 13-bits transfer
  • 6 14-bits transfer
  • 7 15-bits transfer
  • 8 16-bits transfer
CSMODE5:4Chip Select Mode
  • 0 The chip select is deasserted if TD has not been reloaded before the end of the current transfer.
  • 1 The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.
  • 2 The chip select is deasserted systematically after each transfer.
SMEMREG3Serial Memory reg
WDRBT2Wait Data Read Before Transfer
LOOPEN1Local Loopback Enable
  • 0 Local Loopback is disabled
  • 1 Local Loopback is enabled
MODE0Serial Memory Mode
  • 0 SPI operating mode
  • 1 Serial Memory operating mode
DLYCS31:24Minimum Inactive CS Delay

BAUDBaud Rate

Address
0x42000008
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SCK
BAUD15:8Serial Clock Baud Rate
CPHA1Clock Phase
CPOL0Clock Polarity

RXDATAReceive Data

Address
0x4200000C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
DATA15:0Receive Data

TXDATATransmit Data

Address
0x42000010
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
DATA15:0Transmit Data

INTENCLRInterrupt Enable Clear

Address
0x42000014
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
INSTREND10Instruction End Interrupt Disable
CSRISE8Chip Select Rise Interrupt Disable
ERROR3Overrun Error Interrupt Disable
TXC2Transmission Complete Interrupt Disable
DRE1Transmit Data Register Empty Interrupt Disable
RXC0Receive Data Register Full Interrupt Disable

INTENSETInterrupt Enable Set

Address
0x42000018
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
INSTREND10Instruction End Interrupt Enable
CSRISE8Chip Select Rise Interrupt Enable
ERROR3Overrun Error Interrupt Enable
TXC2Transmission Complete Interrupt Enable
DRE1Transmit Data Register Empty Interrupt Enable
RXC0Receive Data Register Full Interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x4200001C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
INSTREND10Instruction End
CSRISE8Chip Select Rise
ERROR3Overrun Error
TXC2Transmission Complete
DRE1Transmit Data Register Empty
RXC0Receive Data Register Full

STATUSStatus Register

Address
0x42000020
Reset
0x00000200
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
CSSTATUS9Chip Select
ENABLE1Enable

INSTRADDRInstruction Address

Address
0x42000030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDR31:0Instruction Address

INSTRCTRLInstruction Code

Address
0x42000034
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
OPTCODE23:16Option Code
INSTR7:0Instruction Code

INSTRFRAMEInstruction Frame

Address
0x42000038
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
DUMMYLEN20:16Dummy Cycles Length
DDREN15Double Data Rate Enable
CRMODE14Continuous Read Mode
TFRTYPE13:12Data Transfer Type
  • 0 Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible.
  • 1 Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible.
  • 2 Write transfer into the serial memory.Scrambling is not performed.
  • 3 Write data transfer into the serial memory.If enabled, scrambling is performed.
ADDRLEN10Address Length
  • 0 24-bits address length
  • 1 32-bits address length
OPTCODELEN9:8Option Code Length
  • 0 1-bit length option code
  • 1 2-bits length option code
  • 2 4-bits length option code
  • 3 8-bits length option code
DATAEN7Data Enable
OPTCODEEN6Option Enable
ADDREN5Address Enable
INSTREN4Instruction Enable
WIDTH2:0Instruction Code, Address, Option Code and Data Width
  • 0 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
  • 1 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
  • 2 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
  • 3 Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
  • 4 Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
  • 5 Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
  • 6 Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI

SCRAMBCTRLScrambling Mode

Address
0x42000040
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
RANDOMDIS1Scrambling/Unscrambling Random Value Disable
ENABLE0Scrambling/Unscrambling Enable

SCRAMBKEYScrambling Key

Address
0x42000044
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
KEY31:0Scrambling User Key