The 3 registers of CRU (Oscillator and clocks), from 0xBF801240, with their reset value and every field. The WFI32E01 has 1091 registers in 66 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CRU Oscillator and clocks
BTPLLCONBTPLL CONTROL REGISTER
Address
0xBF801240
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
BTPLLCLK
30
Source Input Clock Selection bit
0 POSC is the BTPLL input clock source.
1 FRC is the BTPLL input clock source.
BTLOCK
29
BT PLL Lock Status bit (Read-only)
0 Indicates that BTPLL is out of lock, start-up timer is in progress, or is turned-off.
1 Indicates that BTPLL is in lock.
BTCLKOUTEN
28
BT Clock Out pin Enable Bit
0 BT_CLK_OUT Pin is disabled
1 BT_CLK_OUT Pin is enabled
BTPLLREFDIV
27:22
Reference Frequency Divide
BTPLLFBDIV
21:12
PLL feedback divider
BTPLLRST
11
BT PLL Reset
0 De-assert the reset to the BTPLL
1 Assert the reset to the BTPLL
BTPLLFLOCK
10
BT PLL Force Lock
0 Do not force the BTPLL lock signal to be asserted
1 Force the BTPLL lock signal to be asserted
BTPLLPOSTDIV1
9:4
First Post Divide Value. 1 to 63
BTPLLPWDN
3
PLL Power Down Register bit
0 PLL is active
1 PLL is powered down
BTPLLBSWSEL
2:0
PLL Bandwidth Select
BTPLL_BYP
31
BTPLL Bypass
0 input clock REF does not bypass PLL to PLLOUTx
1 input clock REF bypasses PLL to PLLOUTx
EWPLLCONEWPLL CONTROL REGISTER
Address
0xBF801250
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
EWPLLICLK
30
Source Input Clock Selection bit
0 POSC is the EWPLL input clock source.
1 FRC is the EWPLL input clock source.
EWLOCK
29
EW PLL Lock Status bit (Read-only)
0 Indicates that EWPLL is out of lock, start-up timer is in progress, or is turned-off.
1 Indicates that EWPLL is in lock.
ETHCLKOUTEN
28
Ethernet Clock Out pin Enable Bit
0 ETH_CLK_OUT Pin is disabled
1 ETH_CLK_OUT Pin is enabled
EWPLLREFDIV
27:22
Reference Frequency Divide
EWPLLFBDIV
21:12
PLL feedback divider
EWPLLRST
11
EW PLL Reset
0 De-assert the reset to the EWPLL
1 Assert the reset to the EWPLL
EWPLLFLOCK
10
EW PLL Force Lock
0 Do not force the EWPLL lock signal to be asserted
1 Force the EWPLL lock signal to be asserted
EWPLLPOSTDIV1
9:4
First Post Divide Value
EWPLLPWDN
3
PLL Power Down Register bit
0 PLL is active
1 PLL is powered down
EWPLLBSWSEL
2:0
PLL Bandwidth Select
EWPLL_BYP
31
EWPLL Bypass
0 the input clock REF does not bypass PLL to PLLOUTx
BETA