WFI32E01 CRYPTO registers The 25 registers of CRYPTO (Crypto engine), from 0xBF8E4000, with their reset value and every field. The WFI32E01 has 1091 registers in 66 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CRYPTO Crypto engine CEVERCrypto Engine Revision
Address 0xBF8E4000
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does VERSION 23:16 ID 15:0 REVISION 31:24
CECONCrypto Engine Control Register
Address 0xBF8E4004
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does SWAPOEN 7 Swap Output Data Enable bit0 Output data is not byte swapped when written by dedicated DMA1 Output data is byte swapped when written by dedicated DMA SWRST 6 Software Reset bit0 Normal operation1 Initiate a software reset of the Crypto Engine SWAPEN 5 Input Data Swap Enable bit0 Input data is not byte swapped when read by dedicated DMA1 Input data is byte swapped when read by dedicated DMA BDPCHST 2 Buffer Descriptor Processor Fetch Enable bit0 BDP descriptor fetch is disabled1 BDP descriptor fetch is enabled BDPPLEN 1 Buffer Descriptor Processor Poll Enable bit0 Do not poll1 Poll for descriptor until valid bit is set DMAEN 0 DMA Enable bit0 Crypto Engine DMA is disabled1 Crypto Engine DMA is enabled
CEBDADDRCrypto Engine Buffer Descriptor Register
Address 0xBF8E4008
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BDPADDR 31:0
CEBDPADDRCrypto Engine Buffer Descriptor Processor Register
Address 0xBF8E400C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BASEADDR 31:0
CESTATCrypto Engine Status Register
Address 0xBF8E4010
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ERROP 28:26 Internal Error Operation Status bits0 Reserved1 Encryption2 Decryption3 Reserved4 Authentication5 Reserved6 Reserved7 Reserved ERRPHASE 25:24 Internal Error Phase of DMA Status bits0 Buffer Descriptor (BD) access1 Security Association (SA) access2 Source data3 Destination data BDSTATE 21:18 Buffer Descriptor Processor State Status bits0 BDP is idle1 Descriptor fetch request is pending2 BDP is loading3 Data phase4 Descriptor is done5 Fetch BDP is disabled6 SA fetch7 Reserved8 Reserved9 Reserved10 Reserved11 Reserved12 Reserved13 Reserved14 Reserved15 Reserved START 17 DMA Start Status bit0 DMA start has not occurred1 DMA start has occurred ACTIVE 16 Buffer Descriptor Processor Status bit0 BDP is idle1 BDP is active BDCTRL 15:0 ERRMODE 31:29 Internal Error Mode Status bits0 Normal operation1 Preboot authentication2 KEK operation3 CEK operation4 Reserved5 Reserved6 Reserved7 Reserved
CEINTSRCCrypto Engine Interrupt Source Register
Address 0xBF8E4014
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does AREIF 3 Access Response Error Interrupt bit0 No error has occurred1 Error occurred trying to access memory outside the Crypto Engine PKTIF 2 DMA Packet Completion Interrupt Status bit0 DMA packet was not completed1 DMA packet was completed CBDIF 1 BD Transmit Status bit0 Last BD transmit has not been processed1 Last BD transmit was processed PENDIF 0 Crypto Engine Interrupt Pending Status bit0 Crypto Engine interrupt is not pending1 Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine)
CEINTENCrypto Engine Interrupt Enable Register
Address 0xBF8E4018
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does AREIE 3 Access Response Error Interrupt Enable bit0 Access response error interrupts are not enabled1 Access response error interrupts are enabled PKTIE 2 DMA Packet Completion Interrupt Enable bit0 DMA packet completion interrupts are not enabled1 DMA packet completion interrupts are enabled CBDIE 1 PENDIE 0 Master Interrupt Enable bit0 Crypto Engine interrupts are not enabled1 Crypto Engine interrupts are enabled
CEPOLLCONCrypto Engine Poll Control Register
Address 0xBF8E401C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BDPPLCON 15:0
CEHDLENCrypto Engine Header Length Register
Address 0xBF8E4020
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does HDRLEN 7:0
CETRLLENCrypto Engine Trailer Length Register
Address 0xBF8E4024
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TRLRLEN 7:0
CEDTXSTAT
Address 0xBF8E4028
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DTXBLEN 19:4 DTXSTATE 3:0
CEDRXSTAT
Address 0xBF8E402C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DRXBLEN 19:4 DRXSTATE 3:0
CEDCRYPTOADDR
Address 0xBF8E4030
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CRYPTOADDR 3:0
CEDHASHADDR
Address 0xBF8E4034
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does HASHADDR 3:0
CEDTXADDR
Address 0xBF8E4038
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does TXDADDR 1:0
CEDML0ADDR
Address 0xBF8E403C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does ML0ADDR 31:0
CEDML1ADDR
Address 0xBF8E4040
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does ML1ADDR 31:0
CEDOL0ADDR
Address 0xBF8E4044
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does OL0ADDR 31:0
CEDCSTADDDR
Address 0xBF8E4048
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CSTATEADDR 3:0
CEDMTSKADDR
Address 0xBF8E404C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does MTASKADDR 1:0
CEDSACON
Address 0xBF8E4050
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does SACON 31:0
CEDCSTATE
Address 0xBF8E4054
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CSTATE 3:0
CEDTXBCNT
Address 0xBF8E4058
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CTXBCNT 4:0
CEDRXBCNT
Address 0xBF8E405C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does DRXBCNT 6:0
CEREV
Address 0xBF8E4060
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does MAINTENANCE 23:16 MINOR 15:8 MAJOR 7:0
BETA