WFI32E01 DCH0 registers

The 12 registers of DCH0 (DMA channel 0), from 0xBF811060, with their reset value and every field. The WFI32E01 has 1091 registers in 66 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

DCH0 DMA channel 0

DCH0CONDMA Channel x Control Register

Address
0xBF811060
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
CHBUSY15Channel Busy bit
  • 0 Channel is inactive or has been disabled
  • 1 Channel is active or has been enabled
CHPIGNEN13Enable Pattern Ignore Byte bit
  • 0 Disable this feature
  • 1 Treat any byte that matches the CHPIGN bits as a dont care when pattern matching is enabled
CHPATLEN11Pattern Length bit
  • 0 1 byte length
  • 1 2 byte length
CHCHNS8Chain Channel Selection bit
  • 0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
  • 1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN7Channel Enable bit
  • 0 Channel is disabled
  • 1 Channel is enabled
CHAED6Channel Allow Events If Disabled bit
  • 0 Channel start/abort events will be ignored if the channel is disabled
  • 1 Channel start/abort events will be registered
CHCHN5Channel Chain Enable bit
  • 0 Do not allow channel to be chained
  • 1 Allow channel to be chained
CHAEN4Channel Automatic Enable bit
  • 0 Channel is disabled on block transfer complete
  • 1 Channel is continuously enabled
CHEDET2Channel Event Detected bit
  • 0 No events have been detected
  • 1 An event has been detected
CHPRI1:0Channel Priority bits
  • 0 Channel has priority 0
  • 1 Channel has priority 1
  • 2 Channel has priority 2
  • 3 Channel has priority 3 (highest)
CHPIGN31:24

DCH0ECONDMA Channel x Event Control Register

Address
0xBF811070
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
CHAIRQ23:16Channel Transfer Abort IRQ bits
  • 0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
  • 1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
  • 255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ15:8Channel Transfer Start IRQ bits
  • 0 Interrupt 0 will initiate a DMA transfer
  • 1 Interrupt 1 will initiate a DMA transfer
  • 255 Interrupt 255 will initiate a DMA transfer
CFORCE7DMA Forced Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT6DMA Abort Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is aborted when this bit is written to a 1
PATEN5Channel Pattern Match Abort Enable bit
  • 0 Pattern match is disabled
  • 1 Abort transfer and clear CHEN on pattern match
SIRQEN4Channel Start IRQ Enable bit
  • 0 Interrupt number CHSIRQ is ignored and does not start a transfer
  • 1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN3Channel Abort IRQ Enable bit
  • 0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
  • 1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs

DCH0INTDMA Channel x Interrupt Control Register

Address
0xBF811080
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
CHSDIE23Channel Source Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSHIE22Channel Source Half Empty Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDDIE21Channel Destination Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDHIE20Channel Destination Half Full Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHBCIE19Channel Block Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHCCIE18Channel Cell Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHTAIE17Channel Transfer Abort Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHERIE16Channel Address Error Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSDIF7Channel Source Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF6Channel Source Half Empty Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF5Channel Destination Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF4Channel Destination Half Full Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF3Channel Block Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred)
CHCCIF2Channel Cell Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF1Channel Transfer Abort Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF0Channel Address Error Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A channel address error has been detected Either the source or the destination address is invalid.

DCH0SSADMA Channel x Source Start Address Register

Address
0xBF811090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHSSA31:0

DCH0DSADMA Channel x Destination Start Address Register

Address
0xBF8110A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHDSA31:0

DCH0SSIZDMA Channel x Source Size Register

Address
0xBF8110B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHSSIZ15:0Channel Source Size bits
  • 0 65536 byte source size
  • 1 1 byte source size
  • 2 2 byte source size

DCH0DSIZDMA Channel x Destination Size Register

Address
0xBF8110C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHDSIZ15:0Channel Destination Size bits
  • 0 65536 byte destination size
  • 1 1 byte destination size
  • 2 2 byte destination size

DCH0SPTRDMA Channel x Source Pointer Register

Address
0xBF8110D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHSPTR15:0Channel Source Pointer bits
  • 0 Points to byte 0 of the source
  • 1 Points to byte 1 of the source
  • 65535 Points to byte 65535 of the source

DCH0DPTRDMA Channel x Destination Pointer Register

Address
0xBF8110E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHDPTR15:0Channel Destination Pointer bits
  • 0 Points to byte 0 of the destination
  • 1 Points to byte 1 of the destination
  • 65535 Points to byte 65535 of the destination

DCH0CSIZDMA Channel x Cell-Size Register

Address
0xBF8110F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHCSIZ15:0Channel Cell-Size bits
  • 0 65536 bytes transferred on an event
  • 1 1 byte transferred on an event
  • 2 2 bytes transferred on an event
  • 65535 65535 bytes transferred on an event

DCH0CPTRDMA Channel x Cell Pointer Register

Address
0xBF811100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHCPTR15:0Channel Cell Progress Pointer bits
  • 0 0 bytes have been transferred since the last event
  • 1 1 byte has been transferred since the last event
  • 65535 65535 bytes have been transferred since the last event

DCH0DATDMA Channel x Pattern Data Register

Address
0xBF811110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHPDAT15:0