WFI32E02 OSC registers

The 13 registers of OSC (Oscillator and clocks), from 0xBF801200, with their reset value and every field. The WFI32E02 has 1091 registers in 66 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

OSC Oscillator and clocks

OSCCONCRU OSCILLATOR CONTROL REGISTER

Address
0xBF801200
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FRCDIV26:24Fast RC Clock Divider bits
  • 0 FRC Divide by 1
  • 1 FRC Divide by 2
  • 2 FRC Divide by 4
  • 3 FRC Divide by 8
  • 4 FRC Divide by 16
  • 5 FRC Divide by 32
  • 6 FRC Divide by 64
  • 7 FRC Divide by 256
DRMEN23Enable Dream Mode bit
  • 0 DMA transfer has no effect
  • 1 When the cpu_si_sleep input is asserted and SLPEN = 1, DMA transfer complete causes SLEEP Mode to be entered
WAKE2SPD212-Speed startup enabled in Sleep mode bit
  • 0 When the device EXITS Sleep Mode, the sys_clk will be from the selected clock.
  • 1 When the device EXITS Sleep Mode, the sys_clk will be from FRC until the selected clock is ready
COSC15:12Current Oscillator Selection bits (Read-only)
  • 0 Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV (Supports FRC/16 and FRC/1)
  • 1 System PLL (SPLL Module) (input clock and divider set by SPLLCON)
  • 2 Primary Oscillator- POSC
  • 3 USB PLL (UPLL Module) (input clock and divider set by UPLLCON)
  • 4 Secondary Oscillator (SOSC)
  • 5 Low Power RC Oscillator (LPRC)
  • 6 BT PLL (input clock and divider set by BTPLLCON)
  • 7 EWPLL Ethernet Clock (input clock and divider set by EWPLLCON)
  • 8 EWPLL WiFi Clock (input clock and divider set by EWPLLCON)
NOSC11:8New Oscillator Selection bits
  • 0 Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV ( Supports FRC/16 and FRC/1)
  • 1 SPLL Module (input clock and divider set by SPLLCON)
  • 2 Primary Oscillator
  • 3 UPLL mode (input clock divider set by UPLLCON) -- was POSC with PLL
  • 4 Secondary Oscillator (SOSC)
  • 5 Low Power RC Oscillator (LPRC)
  • 6 BT PLL (input clock and divider set by BTPLLCON)
  • 7 EWPLL Ethernet Clock (input clock and divider set by EWPLLCON)
  • 8 EWPLL WiFi Clock (input clock and divider set by EWPLLCON)
CLKLOCK7Clock Lock Enabled bit
  • 0 Clock and PLL selection registers are not locked, configurations may be modified
  • 1 All clock and PLL configuration registers are locked. These include OSCCON, OSCTRIM, SPLLCON, UPLLCON, PBxDIV
SLPEN4Enable SLEEP Mode bit
  • 0 When a WAIT instruction is executed device will enter IDLE Mode
  • 1 When a WAIT Instruction is executed device will enter SLEEP Mode
CF3Clock Fail Detect bit (Read / writable / Clearable by application)
  • 0 FSCM has not detected clock failure
  • 1 FSCM has detected clock failure
UFRCEN2USB FRC Clock Enable bit
  • 0 Use the primary oscillator or UPLL as the USB clock source
  • 1 Enable FRC as the clock source for the USB clock source
SOSCEN132 kHz Secondary (LP) Oscillator Enable bit
  • 0 Disable Secondary Oscillator
  • 1 Enable Secondary Oscillator
OSWEN0Oscillator Switch Enable bit
  • 0 Oscillator switch is complete
  • 1 Request oscillator switch to selection specified by NOSC[3:0] bits

OSCTUNCRU OSCILLATOR TRIMMING REGISTER

Address
0xBF801210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TUN5:0Internal Fast RC (FRC) Oscillator Tuning bits
  • 0 Center Frequency, oscillator is running at calibrated frequency
  • 31 Maximum Frequency
  • 32 Minimum Frequency

SPLLCONSPLL CONTROL REGISTER

Address
0xBF801220
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
SPLLICLK30Source Input Clock Selection bit
  • 0 POSC is the SPLL input clock source.
  • 1 FRC is the SPLL input clock source.
SLOCK29System PLL Lock Status bit (Read-only)
  • 0 Indicates that SPLL is out of lock, start-up timer is in progress, or is turned-off.
  • 1 Indicates that SPLL is in lock.
SPLLREFDIV27:22Reference Frequency Divide, 1 to 63
SPLLFBDIV21:12PLL feedback divider, 16 to 1023
SPLLRST11System PLL Reset
  • 0 De-assert the reset to the SPLL
  • 1 Assert the reset to the SPLL
SPLLFLOCK10System PLL Force Lock
  • 0 Do not force the SPLL lock signal to be asserted
  • 1 Force the SPLL lock signal to be asserted
SPLLPOSTDIV19:4First Post Divide Value, 1 to 63
SPLLPWDN3PLL Power Down Register bit
  • 0 PLL is active
  • 1 PLL is powered down
SPLLBSWSEL2:0PLL Bandwidth Select
SPLL_BYP31SPLL Bypass
  • 0 The input clock REF does not bypass PLL to PLLOUTx
  • 1 The input clock REF bypasses PLL to PLLOUTx

UPLLCONUPLL CONTROL REGISTER

Address
0xBF801230
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
ULOCK29USB PLL Lock Status bit (Read-only)
  • 0 Indicates that UPLL is out of lock, start-up timer is in progress, or is turned-off.
  • 1 Indicates that UPLL is in lock.
UPLLREFDIV27:22Reference Frequency Divide. 1 to 63
UPLLFBDIV21:12PLL feedback divider, 16 to 1023
UPLLRST11USB PLL Reset
  • 0 De-assert the reset to the UPLL
  • 1 Assert the reset to the UPLL
UPLLFLOCK10USB PLL Force Lock
  • 0 Do not force the UPLL lock signal to be asserted
  • 1 Force the UPLL lock signal to be asserted
UPLLPOSTDIV19:4First Post Divide Value, 1 to 63
UPLLPWDN3PLL Power Down Register bit
  • 0 PLL is active
  • 1 PLL is powered down
UPLLBSWSEL2:0USB PLL Bandwidth Select
UPLL_BYP31UPLL Bypass
  • 0 the input clock REF does not bypass PLL to PLLOUTx
  • 1 the input clock REF bypasses PLL to PLLOUTx

PB1DIVPB1 CLOCK DIVISOR CONTROL REGISTER

Address
0xBF801320
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PB1DIVON15
PBDIVRDY11PB1 Peripheral Clock Divisor Ready
  • 0 Indicates the PB clock divisor logic is currently switching values and the PB1DIV cannot be written.
  • 1 Indicates the PB clock divisor logic is not switching divisors and the PB1DIV may be written.
PBDIV6:0PB1 Peripheral Clock Divisor Control value
  • 0 Divide by 1 PB1 Clock same frequency as sys_clk
  • 1 Divide by 2 PB1 Clock is 1/2 of sys_clk
  • 2 Divide by 3 PB1 Clock is 1/3 of sys_clk
  • 15 Divide by 16 PB1 Clock is 1/16 of sys_clk
  • 16 Divide by 17 PB1 Clock is 1/17 of sys_clk
  • 126 Divide by 127 PB1 Clock is 1/127 of sys_clk
  • 127 Divide by 128 PB1 Clock is 1/128 of sys_clk

PB2DIVPB2 CLOCK DIVISOR CONTROL REGISTER

Address
0xBF801330
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PB2DIVON15
PBDIVRDY11PB2 Peripheral Clock Divisor Ready
  • 0 Indicates the PB clock divisor logic is currently switching values and the PB2DIV cannot be written.
  • 1 Indicates the PB clock divisor logic is not switching divisors and the PB2DIV may be written.
PBDIV6:0PB2 Peripheral Clock Divisor Control value
  • 0 Divide by 1 PB2 Clock same frequency as sys_clk
  • 1 Divide by 2 PB2 Clock is 1/2 of sys_clk
  • 2 Divide by 3 PB2 Clock is 1/3 of sys_clk
  • 15 Divide by 16 PB2 Clock is 1/16 of sys_clk
  • 16 Divide by 17 PB2 Clock is 1/17 of sys_clk
  • 126 Divide by 127 PB2 Clock is 1/127 of sys_clk
  • 127 Divide by 128 PB2 Clock is 1/128 of sys_clk

PB3DIVPB3 CLOCK DIVISOR CONTROL REGISTER

Address
0xBF801340
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PB3DIVON15
PBDIVRDY11PB3 Peripheral Clock Divisor Ready
  • 0 Indicates the PB clock divisor logic is currently switching values and the PB3DIV cannot be written.
  • 1 Indicates the PB clock divisor logic is not switching divisors and the PB3DIV may be written.
PBDIV6:0PB3 Peripheral Clock Divisor Control value
  • 0 Divide by 1 PB3 Clock same frequency as sys_clk
  • 1 Divide by 2 PB3 Clock is 1/2 of sys_clk
  • 2 Divide by 3 PB3 Clock is 1/3 of sys_clk
  • 15 Divide by 16 PB3 Clock is 1/16 of sys_clk
  • 16 Divide by 17 PB3 Clock is 1/17 of sys_clk
  • 126 Divide by 127 PB3 Clock is 1/127 of sys_clk
  • 127 Divide by 128 PB3 Clock is 1/128 of sys_clk

PB4DIVPB4 CLOCK DIVISOR CONTROL REGISTER

Address
0xBF801350
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PB4DIVON15
PBDIVRDY11PB4 Peripheral Clock Divisor Ready
  • 0 Indicates the PB clock divisor logic is currently switching values and the PB4DIV cannot be written.
  • 1 Indicates the PB clock divisor logic is not switching divisors and the PB4DIV may be written.
PBDIV6:0PB4 Peripheral Clock Divisor Control value
  • 0 Divide by 1 PB4 Clock same frequency as sys_clk
  • 1 Divide by 2 PB4 Clock is 1/2 of sys_clk
  • 2 Divide by 3 PB4 Clock is 1/3 of sys_clk
  • 15 Divide by 16 PB4 Clock is 1/16 of sys_clk
  • 16 Divide by 17 PB4 Clock is 1/17 of sys_clk
  • 126 Divide by 127 PB4 Clock is 1/127 of sys_clk
  • 127 Divide by 128 PB4 Clock is 1/128 of sys_clk

PB5DIVPB5 CLOCK DIVISOR CONTROL REGISTER

Address
0xBF801360
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PB5DIVON15
PBDIVRDY11PB5 Peripheral Clock Divisor Ready
  • 0 Indicates the PB clock divisor logic is currently switching values and the PB5DIV cannot be written.
  • 1 Indicates the PB clock divisor logic is not switching divisors and the PB5DIV may be written.
PBDIV6:0PB5 Peripheral Clock Divisor Control value
  • 0 Divide by 1 PB5 Clock same frequency as sys_clk
  • 1 Divide by 2 PB5 Clock is 1/2 of sys_clk
  • 2 Divide by 3 PB5 Clock is 1/3 of sys_clk
  • 15 Divide by 16 PB5 Clock is 1/16 of sys_clk
  • 16 Divide by 17 PB5 Clock is 1/17 of sys_clk
  • 126 Divide by 127 PB5 Clock is 1/127 of sys_clk
  • 127 Divide by 128 PB5 Clock is 1/128 of sys_clk

PB6DIVPB6 CLOCK DIVISOR CONTROL REGISTER

Address
0xBF801370
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PB6DIVON15
PBDIVRDY11PB6 Peripheral Clock Divisor Ready
  • 0 Indicates the PB clock divisor logic is currently switching values and the PB6DIV cannot be written.
  • 1 Indicates the PB clock divisor logic is not switching divisors and the PB6DIV may be written.
PBDIV6:0PB6 Peripheral Clock Divisor Control value
  • 0 Divide by 1 PB6 Clock same frequency as sys_clk
  • 1 Divide by 2 PB6 Clock is 1/2 of sys_clk
  • 2 Divide by 3 PB6 Clock is 1/3 of sys_clk
  • 15 Divide by 16 PB6 Clock is 1/16 of sys_clk
  • 16 Divide by 17 PB6 Clock is 1/17 of sys_clk
  • 126 Divide by 127 PB6 Clock is 1/127 of sys_clk
  • 127 Divide by 128 PB6 Clock is 1/128 of sys_clk

SLEWCONSLEW RATE CONTROL FOR CLOCK SWITCHING REGISTER

Address
0xBF801380
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
SLWDLY27:24Number of clocks generated at each slew step for a clock switch
  • 0 1 clock will be generated at each slew step
  • 1 2 clocks will be generated at each slew step
  • 2 3 clocks will be generated at each slew step
  • 3 4 clocks will be generated at each slew step
  • 4 5 clocks will be generated at each slew step
  • 5 6 clocks will be generated at each slew step
  • 6 7 clocks will be generated at each slew step
  • 7 8 clocks will be generated at each slew step
  • 8 9 clocks will be generated at each slew step
  • 9 10 clocks will be generated at each slew step
  • 10 11 clocks will be generated at each slew step
  • 11 12 clocks will be generated at each slew step
  • 12 13 clocks will be generated at each slew step
  • 13 14 clocks will be generated at each slew step
  • 14 15 clocks will be generated at each slew step
  • 15 16 clocks will be generated at each slew step
SYSDIV19:16PBx Peripheral Clock Divisor Control value
  • 0 Divide by 1- sys_clk_out same frequency as sys_clk source - Default
  • 1 Divide by 2- sys_clk_out is 1/2 of sys_clk source
  • 2 Divide by 3- sys_clk_out is 1/3 of sys_clk source
  • 3 Divide by 4- sys_clk_out is 1/4 of sys_clk source
  • 4 Divide by 5- sys_clk_out is 1/5 of sys_clk source
  • 5 Divide by 6- sys_clk_out is 1/6 of sys_clk source
  • 6 Divide by 7- sys_clk_out is 1/7 of sys_clk source
  • 7 Divide by 8- sys_clk_out is 1/8 of sys_clk source
  • 8 Divide by 9- sys_clk_out is 1/9 of sys_clk source
  • 9 Divide by 10- sys_clk_out is 1/10 of sys_clk source
  • 10 Divide by 11- sys_clk_out is 1/11 of sys_clk source
  • 11 Divide by 12- sys_clk_out is 1/12 of sys_clk source
  • 12 Divide by 13- sys_clk_out is 1/13 of sys_clk source
  • 13 Divide by 14- sys_clk_out is 1/14 of sys_clk source
  • 14 Divide by 15- sys_clk_out is 1/15 of sys_clk source
  • 15 Divide by 16- sys_clk_out is 1/16 of sys_clk source
SLWDIV10:8Divisor steps used when doing slewed clock switches
  • 0 No Divisor used
  • 1 Divide by 2, then no divisor
  • 2 Divide by 4, then by 2, then no divisor
  • 3 Divide by 8, then by 4, then by 2, then no divisor
  • 4 Divide by 16, then by 8, then by 4, then by 2, then no divisor
  • 5 Divide by 32, then by 16, then by 8, then by 4, then by 2, then no divisor
  • 6 Divide by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor
  • 7 Divide by 128, then by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor
UPEN2Clock slew enable for switching up to faster clocks
  • 0 Clock Slewing disabled
  • 1 Clock Slewing enabled on a clock switch OR exit from SLEEP
DNEN1Clock slew enable for switching down to slower clocks
  • 0 Clock Slewing disabled
  • 1 Clock Slewing enabled on a clock switch
BUSY0Clock Switch Slewing Active Status Bit - Read-Only
  • 0 Clock Switch has reached its final value
  • 1 Clock frequency is being actively Slewed

CLKSTATCLOCK STATUS REGISTER

Address
0xBF801390
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
SYSCLKRDY11System Clock Ready Status value
  • 0 SYSCLK is not stable and not ready
  • 1 SYSCLK is stable and ready
PB1CLKRDY10PB1 Clock Ready Status value
  • 0 PB1CLK is not stable and not ready
  • 1 PB1CLK is stable and ready
SPLLALTRDY9System PLL Ready Status value
  • 0 SPLL Alternate Output is not stable and not ready
  • 1 SPLL Alternate Output is stable and ready
WIFICLKRDY8WiFi Clock Ready Status value
  • 0 WIFICLK is not stable and not ready
  • 1 WIFICLK is stable and ready
ETHPLLRDY7EWPLL Ready Status value
  • 0 EWPLL is not stable and not ready
  • 1 EWPLL is stable and ready
BTPLLRDY6Bluetooth PLL Ready Status value
  • 0 BTPLL is not stable and not ready
  • 1 BTPLL is stable and ready
LPRCRDY5LPRC Ready Status value
  • 0 LPRC is not stable and not ready
  • 1 LPRC is stable and ready
SOSCRDY4SOSC Ready Status value
  • 0 SOSC is not stable and not ready
  • 1 SOSC is stable and ready
UPLLRDY3USB PLL Ready Status value
  • 0 UPLL is not stable and not ready
  • 1 UPLL is stable and ready
POSCRDY2Primary Oscillator Ready Status value
  • 0 POSC is not stable and not ready
  • 1 POSC is stable and ready
SPLLRDY1System PLL Ready Status value
  • 0 SPLL Primary Output is not stable and not ready
  • 1 SPLL Primary Output is stable and ready
FRCRDY0FRC Ready Status value
  • 0 FRC is not stable and not ready
  • 1 FRC is stable and ready

OSCCONBAR

Address
0xBF8013A0
Reset
0x00000000
Access
read/write
Size
32-bit