Hello Mentees! I hope you all are doing well. In today's article, we'll learn about the very basic pillar of Digital Logic Circuits i.e. Logic Gates. As we know, the digital world depends on Boolean digits either 0 or 1. So, there's always a need to perform different operations on these boolean numbers i.e. addition, subtraction, multiplication, shifting etc. In order to perform these operations on the binary signals, we use Digital Logic Gates in DLD circuits.
So, let's have a look at What is a Logic Gate:
Input |
Output |
0 | 1 |
1 |
0 |
Truth tables are useful in Boolean and mathematical operations as the relationship between the Input and Output can be understood at a glance.
Now let's have a look at the Circuit Designing of Logic Gates:
As we discussed earlier, different Manufacturing Techniques are used to design logic gates. These techniques decide the characteristics of the logic gates i.e.
response time, noise immunity, voltage level for logic shifting etc. We can use simple electronic components i.e. diode, transistor, resistor etc. to design logic gates. The normal practices for designing logic gates with simple electronic components are:
Such logic gates are quite simple in designing and normally have quite low response time and may also provide false output because of noise. So, in order to overcome these issues, these two manufacturing techniques are used:
Simple NPN and PNP transistors are used in TTL logic gates and thus have better response time as compared to basic logic gates. In the CMOS technique, MOSFET and FET are used to control the logic and thus provide the best response time and are quite immune to noise. So, among all these manufacturing techniques, CMOS is considered the most popular technique for logic gate designing.
Here is an example of an AND Gate design with a Diode-Resistor Logic(DRL) and a NAND gate designed with Diode-Transistor Logic (DTL):
As you can see in the above figure, these circuits are quite easy to design, as simply using diodes, resistors, and transistors. But these circuits are not used in commercial ICs because of their high power loss(pull-up resistor) and gate delay(propagation delay). That's why, CMOS and TTL are considered the better option to design digital logic gates.
In TTL Logic Gates, NPN and PNP transistors are used for designing logic gates. The ideal TTL logic gate is the one that gives the LOW(0) Logic at 0V and HIGH(1) Logic at 5V. In a real TTL Logic Gate, the logic will be considered LOW(0), if the voltage level lies between 0-0.8V and the logic will be considered HIGH(1), if the voltage level is in the range of 2-5V. The voltage level between 0.8-2V is considered a "no man's land" and normally external pull-up or pull-down resistors are used to avoid this region. Examples of TTL Logic Gates ICs are 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx, 74ACTxx etc. The switching voltage varies from group to group according to their internal structure and material used.
In CMOS Logic Gates, FET(Field Effect Transistor) and MOSFET are used to design the logic gates. CMOS logic gates provide a LOW(0) logic, if its voltage is in the range of 0-1.5V and it will give HIGH(1) logic, if it's in the range of 3-18V. The below table shows the voltage levels of both TTL and CMOS logic Gates:
Logic Gates |
LOW(0) |
HIGH(1) |
TTL |
0-0.8V |
2-5V |
CMOS |
0-1.5V |
3-18V |
Now, let's have a look at the Types of Logic Gates:
It's quite difficult to cover all these gates in a single lecture. So, we will only discuss the basic 7 gates i.e. AND, OR, NOT, NAND, NOR, XOR and XNOR. Today, we will have a brief overview of these 7 logic gates but in the upcoming lectures, we will cover each one of these individually in full detail. Here are the symbols of few logic gates:
So, let's get started:
A | B | A.B |
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
As you can see in the truth table of AND Gate, the Output is 1 only when both of its inputs are 1, otherwise, it's 0.
Proteus has an AND Gate component in its components library. We are going to use it to verify the truth table of AND Gate. We will use the following components for designing this AND Gate Simulation:
Here's the Proteus simulation of all possible states of the AND Gate with 2-inputs:
A | B | A+B |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
In the case of OR Gate, the output is LOW, only when all of its inputs are LOW, otherwise its HIGH.
A | B |
0 | 1 |
1 | 0 |
So, today we discussed the basic logic gates i.e. AND, OR and NOT Gate and simulated them in Proteus. In upcoming lectures, we'll use these gates to design advance gates and circuits. Take care!!!
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