Hey pals, we hope you are doing well. In our previous lecture, we discussed the basic DLD Basic Logic Gates and simulated in Proteus. Today, we are going to discuss another logic gate called Exclusive OR Gate(XOR Gate). We will also design the XOR Gate in Proteus using the basic logic gates(i.e. AND, OR and NOT), discussed in the previous lecture.
In today's tutorial, we are going to focus on:
A | B | |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
Its definition has two conditions in it:
We have seen in the 2-Input XOR truth table, the output is HIGH in the 2nd and 3rd Rows, because these rows are fulfills both conditions i.e., we have an odd no of HIGH inputs(1 input is HIGH) and at least 1 LOW input(1 Input is LOW). While, in the 1st and 4th rows, both conditions are unfulfilled, thus getting LOW at the output.
Now, let's have a look at the truth table of the 3-input XOR Gate:
Image
Now it will get more clear, as you can see in the 4th row, we have 1 HIGH Input and 2 LOW Inputs, thus both conditions are fulfilled and we are getting HIGH at the OUTPUT. But in the 7th row, 2 Inputs are HIGH and 1 is LOW, although the 2nd condition is fulfilled i.e. we have at least 1 LOW input but the first condition is unfulfilled i.e. we have even no of HIGH Inputs. That's why we are getting LOW at the output. I hope now it gets clear.
Now let's understand the output of the XOR gate mathematically. XOR gate is used in arithmetic calculations because it adds the inputs and gets the carry.
Here's the mathematical calculation of XOR truth table:
0+0=0
0+1=1
1+0=1
1+1=0 (Carry)
Here's the Proteus demonstration of the XOR truth table:
Now, we are going to design an XOR gate using the basic logic gates i.e. AND, OR and NOT. The formula for XOR Gate is as follows:
Y = A.(B)' + (A)'.B
As you can see in the above equation, we can get an XOR output(Y) by applying 3 logic gates i.e. AND, OR and NOT, on the inputs(A and B).
Let's verify this equation by putting values from the XOR truth table:
=0.(0)'+(0)'.0
=0.1+1.0
=0+0
=0
Now, A=0, B=1:
=0.(1)'+(0)'.1
=0.0+1.1
=0+1
=1
Consider A=1, B=0:
=1.(0)'+(1)'.0
=0.1+0.0
=1+0
=1
At last, check the expression when A=1, B=1:
=1.(1)'+(1)'.1
=1.0+0.1
=0+0
=0
So, now let's design this equation for the XOR Gate in the Proteus software. Let's get started:
As we have seen in the previous section, we need to implement this equation in the Proteus software:
Y = A.(B)' + (A)'.B
So, open your Proteus software and get these components from the Proteus library:
Here's the circuit diagram of the XOR Gate in Proteus using the standard logic gates i.e. AND, OR and NOT:
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