ATmega48P registers
All 81 registers by peripheral, at their data-space address (the I/O address IN and OUT use is shown beside it), with their reset value and every bit.
PORTB I/O Port
PINBPort B Input Pins
- Address
0x23 I/O 0x03
- Reset
0x00
- Access
- read/write
- 7PINB7
- 6PINB6
- 5PINB5
- 4PINB4
- 3PINB3
- 2PINB2
- 1PINB1
- 0PINB0
DDRBPort B Data Direction Register
- Address
0x24 I/O 0x04
- Reset
0x00
- Access
- read/write
- 7DDB7
- 6DDB6
- 5DDB5
- 4DDB4
- 3DDB3
- 2DDB2
- 1DDB1
- 0DDB0
PORTBPort B Data Register
- Address
0x25 I/O 0x05
- Reset
0x00
- Access
- read/write
- 7PORTB7
- 6PORTB6
- 5PORTB5
- 4PORTB4
- 3PORTB3
- 2PORTB2
- 1PORTB1
- 0PORTB0
PORTC I/O Port
PINCPort C Input Pins
- Address
0x26 I/O 0x06
- Reset
0x00
- Access
- read/write
- 7–
- 6PINC6
- 5PINC5
- 4PINC4
- 3PINC3
- 2PINC2
- 1PINC1
- 0PINC0
DDRCPort C Data Direction Register
- Address
0x27 I/O 0x07
- Reset
0x00
- Access
- read/write
- 7–
- 6DDC6
- 5DDC5
- 4DDC4
- 3DDC3
- 2DDC2
- 1DDC1
- 0DDC0
PORTCPort C Data Register
- Address
0x28 I/O 0x08
- Reset
0x00
- Access
- read/write
- 7–
- 6PORTC6
- 5PORTC5
- 4PORTC4
- 3PORTC3
- 2PORTC2
- 1PORTC1
- 0PORTC0
PORTD I/O Port
PINDPort D Input Pins
- Address
0x29 I/O 0x09
- Reset
0x00
- Access
- read/write
- 7PIND7
- 6PIND6
- 5PIND5
- 4PIND4
- 3PIND3
- 2PIND2
- 1PIND1
- 0PIND0
DDRDPort D Data Direction Register
- Address
0x2A I/O 0x0A
- Reset
0x00
- Access
- read/write
- 7DDD7
- 6DDD6
- 5DDD5
- 4DDD4
- 3DDD3
- 2DDD2
- 1DDD1
- 0DDD0
PORTDPort D Data Register
- Address
0x2B I/O 0x0B
- Reset
0x00
- Access
- read/write
- 7PORTD7
- 6PORTD6
- 5PORTD5
- 4PORTD4
- 3PORTD3
- 2PORTD2
- 1PORTD1
- 0PORTD0
TC0 Timer/Counter, 8-bit
TIFR0Timer/Counter0 Interrupt Flag register
- Address
0x35 I/O 0x15
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2OCF0B
- 1OCF0A
- 0TOV0
3 fields
| Field | Bits | What it does |
|---|
| OCF0B | 2 | Timer/Counter0 Output Compare Flag 0B |
| OCF0A | 1 | Timer/Counter0 Output Compare Flag 0A |
| TOV0 | 0 | Timer/Counter0 Overflow Flag |
GTCCRGeneral Timer/Counter Control Register
- Address
0x43 I/O 0x23
- Reset
0x00
- Access
- read/write
- 7TSM
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0PSRSYNC
2 fields
| Field | Bits | What it does |
|---|
| TSM | 7 | Timer/Counter Synchronization Mode |
| PSRSYNC | 0 | Prescaler Reset Timer/Counter1 and Timer/Counter0 |
TCCR0ATimer/Counter Control Register A
- Address
0x44 I/O 0x24
- Reset
0x00
- Access
- read/write
- 7COM0A1
- 6COM0A0
- 5COM0B1
- 4COM0B0
- 3–
- 2–
- 1WGM01
- 0WGM00
3 fields
| Field | Bits | What it does |
|---|
| COM0A | 7:6 | Compare Output Mode, Phase Correct PWM Mode |
| COM0B | 5:4 | Compare Output Mode, Fast PWm |
| WGM0 | 1:0 | Waveform Generation Mode |
TCCR0BTimer/Counter Control Register B
- Address
0x45 I/O 0x25
- Reset
0x00
- Access
- read/write
- 7FOC0A
- 6FOC0B
- 5–
- 4–
- 3WGM02
- 2CS02
- 1CS01
- 0CS00
4 fields
| Field | Bits | What it does |
|---|
| FOC0A | 7 | Force Output Compare A |
| FOC0B | 6 | Force Output Compare B |
| WGM02 | 3 | |
| CS0 | 2:0 | Clock Select0 No Clock Source (Stopped)1 Running, No Prescaling2 Running, CLK/83 Running, CLK/644 Running, CLK/2565 Running, CLK/10246 Running, ExtClk Tn Falling Edge7 Running, ExtClk Tn Rising Edge
|
TCNT0Timer/Counter0
- Address
0x46 I/O 0x26
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
OCR0ATimer/Counter0 Output Compare Register
- Address
0x47 I/O 0x27
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
OCR0BTimer/Counter0 Output Compare Register
- Address
0x48 I/O 0x28
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TIMSK0Timer/Counter0 Interrupt Mask Register
- Address
0x6E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2OCIE0B
- 1OCIE0A
- 0TOIE0
3 fields
| Field | Bits | What it does |
|---|
| OCIE0B | 2 | Timer/Counter0 Output Compare Match B Interrupt Enable |
| OCIE0A | 1 | Timer/Counter0 Output Compare Match A Interrupt Enable |
| TOIE0 | 0 | Timer/Counter0 Overflow Interrupt Enable |
TC1 Timer/Counter, 16-bit
TIFR1Timer/Counter Interrupt Flag register
- Address
0x36 I/O 0x16
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5ICF1
- 4–
- 3–
- 2OCF1B
- 1OCF1A
- 0TOV1
4 fields
| Field | Bits | What it does |
|---|
| ICF1 | 5 | Input Capture Flag 1 |
| OCF1B | 2 | Output Compare Flag 1B |
| OCF1A | 1 | Output Compare Flag 1A |
| TOV1 | 0 | Timer/Counter1 Overflow Flag |
GTCCRGeneral Timer/Counter Control Register
- Address
0x43 I/O 0x23
- Reset
0x00
- Access
- read/write
- 7TSM
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0PSRSYNC
2 fields
| Field | Bits | What it does |
|---|
| TSM | 7 | Timer/Counter Synchronization Mode |
| PSRSYNC | 0 | Prescaler Reset Timer/Counter1 and Timer/Counter0 |
TIMSK1Timer/Counter Interrupt Mask Register
- Address
0x6F
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5ICIE1
- 4–
- 3–
- 2OCIE1B
- 1OCIE1A
- 0TOIE1
4 fields
| Field | Bits | What it does |
|---|
| ICIE1 | 5 | Timer/Counter1 Input Capture Interrupt Enable |
| OCIE1B | 2 | Timer/Counter1 Output CompareB Match Interrupt Enable |
| OCIE1A | 1 | Timer/Counter1 Output CompareA Match Interrupt Enable |
| TOIE1 | 0 | Timer/Counter1 Overflow Interrupt Enable |
TCCR1ATimer/Counter1 Control Register A
- Address
0x80
- Reset
0x00
- Access
- read/write
- 7COM1A1
- 6COM1A0
- 5COM1B1
- 4COM1B0
- 3–
- 2–
- 1WGM11
- 0WGM10
3 fields
| Field | Bits | What it does |
|---|
| COM1A | 7:6 | Compare Output Mode 1A, bits |
| COM1B | 5:4 | Compare Output Mode 1B, bits |
| WGM1 | 1:0 | Waveform Generation Mode |
TCCR1BTimer/Counter1 Control Register B
- Address
0x81
- Reset
0x00
- Access
- read/write
- 7ICNC1
- 6ICES1
- 5–
- 4WGM11
- 3WGM10
- 2CS12
- 1CS11
- 0CS10
4 fields
| Field | Bits | What it does |
|---|
| ICNC1 | 7 | Input Capture 1 Noise Canceler |
| ICES1 | 6 | Input Capture 1 Edge Select |
| WGM1 | 4:3 | Waveform Generation Mode |
| CS1 | 2:0 | Prescaler source of Timer/Counter 10 No Clock Source (Stopped)1 Running, No Prescaling2 Running, CLK/83 Running, CLK/644 Running, CLK/2565 Running, CLK/10246 Running, ExtClk Tn Falling Edge7 Running, ExtClk Tn Rising Edge
|
TCCR1CTimer/Counter1 Control Register C
- Address
0x82
- Reset
0x00
- Access
- read/write
- 7FOC1A
- 6FOC1B
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|
| FOC1A | 7 | |
| FOC1B | 6 | |
TCNT1Timer/Counter1 Bytes
- Address
0x84
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
ICR1Timer/Counter1 Input Capture Register Bytes
- Address
0x86
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
OCR1ATimer/Counter1 Output Compare Register Bytes
- Address
0x88
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
OCR1BTimer/Counter1 Output Compare Register Bytes
- Address
0x8A
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
TC2 Timer/Counter, 8-bit Async
TIFR2Timer/Counter Interrupt Flag Register
- Address
0x37 I/O 0x17
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2OCF2B
- 1OCF2A
- 0TOV2
3 fields
| Field | Bits | What it does |
|---|
| OCF2B | 2 | Output Compare Flag 2B |
| OCF2A | 1 | Output Compare Flag 2A |
| TOV2 | 0 | Timer/Counter2 Overflow Flag |
GTCCRGeneral Timer Counter Control register
- Address
0x43 I/O 0x23
- Reset
0x00
- Access
- read/write
- 7TSM
- 6–
- 5–
- 4–
- 3–
- 2–
- 1PSRASY
- 0–
2 fields
| Field | Bits | What it does |
|---|
| TSM | 7 | Timer/Counter Synchronization Mode |
| PSRASY | 1 | Prescaler Reset Timer/Counter2 |
TIMSK2Timer/Counter Interrupt Mask register
- Address
0x70
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2OCIE2B
- 1OCIE2A
- 0TOIE2
3 fields
| Field | Bits | What it does |
|---|
| OCIE2B | 2 | Timer/Counter2 Output Compare Match B Interrupt Enable |
| OCIE2A | 1 | Timer/Counter2 Output Compare Match A Interrupt Enable |
| TOIE2 | 0 | Timer/Counter2 Overflow Interrupt Enable |
TCCR2ATimer/Counter2 Control Register A
- Address
0xB0
- Reset
0x00
- Access
- read/write
- 7COM2A1
- 6COM2A0
- 5COM2B1
- 4COM2B0
- 3–
- 2–
- 1WGM21
- 0WGM20
3 fields
| Field | Bits | What it does |
|---|
| COM2A | 7:6 | Compare Output Mode bits |
| COM2B | 5:4 | Compare Output Mode bits |
| WGM2 | 1:0 | Waveform Generation Mode |
TCCR2BTimer/Counter2 Control Register B
- Address
0xB1
- Reset
0x00
- Access
- read/write
- 7FOC2A
- 6FOC2B
- 5–
- 4–
- 3WGM22
- 2CS22
- 1CS21
- 0CS20
4 fields
| Field | Bits | What it does |
|---|
| FOC2A | 7 | Force Output Compare A |
| FOC2B | 6 | Force Output Compare B |
| WGM22 | 3 | Waveform Generation Mode |
| CS2 | 2:0 | Clock Select bits0 No Clock Source (Stopped)1 Running, No Prescaling2 Running, CLK/83 Running, CLK/324 Running, CLK/645 Running, CLK/1286 Running, CLK/2567 Running, CLK/1024
|
TCNT2Timer/Counter2
- Address
0xB2
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
OCR2ATimer/Counter2 Output Compare Register A
- Address
0xB3
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
OCR2BTimer/Counter2 Output Compare Register B
- Address
0xB4
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
ASSRAsynchronous Status Register
- Address
0xB6
- Reset
0x00
- Access
- read/write
- 7–
- 6EXCLK
- 5AS2
- 4TCN2UB
- 3OCR2AUB
- 2OCR2BUB
- 1TCR2AUB
- 0TCR2BUB
7 fields
| Field | Bits | What it does |
|---|
| EXCLK | 6 | Enable External Clock Input |
| AS2 | 5 | Asynchronous Timer/Counter2 |
| TCN2UB | 4 | Timer/Counter2 Update Busy |
| OCR2AUB | 3 | Output Compare Register2 Update Busy |
| OCR2BUB | 2 | Output Compare Register 2 Update Busy |
| TCR2AUB | 1 | Timer/Counter Control Register2 Update Busy |
| TCR2BUB | 0 | Timer/Counter Control Register2 Update Busy |
EXINT External Interrupts
PCIFRPin Change Interrupt Flag Register
- Address
0x3B I/O 0x1B
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2PCIF2
- 1PCIF1
- 0PCIF0
1 field
| Field | Bits | What it does |
|---|
| PCIF | 2:0 | Pin Change Interrupt Flags |
EIFRExternal Interrupt Flag Register
- Address
0x3C I/O 0x1C
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1INTF1
- 0INTF0
1 field
| Field | Bits | What it does |
|---|
| INTF | 1:0 | External Interrupt Flags |
EIMSKExternal Interrupt Mask Register
- Address
0x3D I/O 0x1D
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1INT1
- 0INT0
1 field
| Field | Bits | What it does |
|---|
| INT | 1:0 | External Interrupt Request 1 Enable |
PCICRPin Change Interrupt Control Register
- Address
0x68
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2PCIE2
- 1PCIE1
- 0PCIE0
1 field
| Field | Bits | What it does |
|---|
| PCIE | 2:0 | Pin Change Interrupt Enables |
EICRAExternal Interrupt Control Register
- Address
0x69
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3ISC11
- 2ISC10
- 1ISC01
- 0ISC00
2 fields
| Field | Bits | What it does |
|---|
| ISC1 | 3:2 | External Interrupt Sense Control 1 Bits0 Low Level of INTX1 Any Logical Change of INTX2 Falling Edge of INTX3 Rising Edge of INTX
|
| ISC0 | 1:0 | External Interrupt Sense Control 0 Bits0 Low Level of INTX1 Any Logical Change of INTX2 Falling Edge of INTX3 Rising Edge of INTX
|
PCMSK0Pin Change Mask Register 0
- Address
0x6B
- Reset
0x00
- Access
- read/write
- 7PCINT7
- 6PCINT6
- 5PCINT5
- 4PCINT4
- 3PCINT3
- 2PCINT2
- 1PCINT1
- 0PCINT0
1 field
| Field | Bits | What it does |
|---|
| PCINT | 7:0 | Pin Change Enable Masks |
PCMSK1Pin Change Mask Register 1
- Address
0x6C
- Reset
0x00
- Access
- read/write
- 7–
- 6PCINT6
- 5PCINT5
- 4PCINT4
- 3PCINT3
- 2PCINT2
- 1PCINT1
- 0PCINT0
1 field
| Field | Bits | What it does |
|---|
| PCINT | 6:0 | Pin Change Enable Masks |
PCMSK2Pin Change Mask Register 2
- Address
0x6D
- Reset
0x00
- Access
- read/write
- 7PCINT7
- 6PCINT6
- 5PCINT5
- 4PCINT4
- 3PCINT3
- 2PCINT2
- 1PCINT1
- 0PCINT0
1 field
| Field | Bits | What it does |
|---|
| PCINT | 7:0 | Pin Change Enable Masks |
CPU CPU Registers
GPIOR0General Purpose I/O Register 0
- Address
0x3E I/O 0x1E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
GPIOR1General Purpose I/O Register 1
- Address
0x4A I/O 0x2A
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
GPIOR2General Purpose I/O Register 2
- Address
0x4B I/O 0x2B
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
SMCRSleep Mode Control Register
- Address
0x53 I/O 0x33
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3SM2
- 2SM1
- 1SM0
- 0SE
2 fields
| Field | Bits | What it does |
|---|
| SM | 3:1 | Sleep Mode Select Bits0 Idle1 ADC Noise Reduction (If Available)2 Power Down3 Power Save4 Reserved5 Reserved6 Standby7 Extended Standby
|
| SE | 0 | Sleep Enable |
MCUSRMCU Status Register
- Address
0x54 I/O 0x34
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3WDRF
- 2BORF
- 1EXTRF
- 0PORF
4 fields
| Field | Bits | What it does |
|---|
| WDRF | 3 | Watchdog Reset Flag |
| BORF | 2 | Brown-out Reset Flag |
| EXTRF | 1 | External Reset Flag |
| PORF | 0 | Power-on reset flag |
MCUCRMCU Control Register
- Address
0x55 I/O 0x35
- Reset
0x00
- Access
- read/write
- 7–
- 6BODS
- 5BODSE
- 4PUD
- 3–
- 2–
- 1–
- 0–
3 fields
| Field | Bits | What it does |
|---|
| BODS | 6 | BOD Sleep |
| BODSE | 5 | BOD Sleep Enable |
| PUD | 4 | |
SPMCSRStore Program Memory Control and Status Register
- Address
0x57 I/O 0x37
- Reset
0x00
- Access
- read/write
- 7SPMIE
- 6RWWSB
- 5–
- 4RWWSRE
- 3BLBSET
- 2PGWRT
- 1PGERS
- 0SELFPRGEN
7 fields
| Field | Bits | What it does |
|---|
| SPMIE | 7 | SPM Interrupt Enable |
| RWWSB | 6 | Read-While-Write Section Busy |
| RWWSRE | 4 | Read-While-Write section read enable |
| BLBSET | 3 | Boot Lock Bit Set |
| PGWRT | 2 | Page Write |
| PGERS | 1 | Page Erase |
| SELFPRGEN | 0 | Self Programming Enable |
SPStack Pointer
- Address
0x5D I/O 0x3D
- Reset
0x02FF
- Access
- read/write
- Size
- 16-bit
SREGStatus Register
- Address
0x5F I/O 0x3F
- Reset
0x00
- Access
- read/write
- 7I
- 6T
- 5H
- 4S
- 3V
- 2N
- 1Z
- 0C
8 fields
| Field | Bits | What it does |
|---|
| I | 7 | Global Interrupt Enable |
| T | 6 | Bit Copy Storage |
| H | 5 | Half Carry Flag |
| S | 4 | Sign Bit |
| V | 3 | Two's Complement Overflow Flag |
| N | 2 | Negative Flag |
| Z | 1 | Zero Flag |
| C | 0 | Carry Flag |
CLKPRClock Prescale Register
- Address
0x61
- Reset
0x00
- Access
- read/write
- 7CLKPCE
- 6–
- 5–
- 4–
- 3CLKPS3
- 2CLKPS2
- 1CLKPS1
- 0CLKPS0
2 fields
| Field | Bits | What it does |
|---|
| CLKPCE | 7 | Clock Prescaler Change Enable |
| CLKPS | 3:0 | Clock Prescaler Select Bits0 11 22 43 84 165 326 647 1288 256
|
PRRPower Reduction Register
- Address
0x64
- Reset
0x00
- Access
- read/write
- 7PRTWI
- 6PRTIM2
- 5PRTIM0
- 4–
- 3PRTIM1
- 2PRSPI
- 1PRUSART0
- 0PRADC
7 fields
| Field | Bits | What it does |
|---|
| PRTWI | 7 | Power Reduction TWI |
| PRTIM2 | 6 | Power Reduction Timer/Counter2 |
| PRTIM0 | 5 | Power Reduction Timer/Counter0 |
| PRTIM1 | 3 | Power Reduction Timer/Counter1 |
| PRSPI | 2 | Power Reduction Serial Peripheral Interface |
| PRUSART0 | 1 | Power Reduction USART |
| PRADC | 0 | Power Reduction ADC |
OSCCALOscillator Calibration Value
- Address
0x66
- Reset
0x00
- Access
- read/write
- 7OSCCAL7
- 6OSCCAL6
- 5OSCCAL5
- 4OSCCAL4
- 3OSCCAL3
- 2OSCCAL2
- 1OSCCAL1
- 0OSCCAL0
1 field
| Field | Bits | What it does |
|---|
| OSCCAL | 7:0 | Oscillator Calibration |
EEPROM EEPROM
EECREEPROM Control Register
- Address
0x3F I/O 0x1F
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5EEPM1
- 4EEPM0
- 3EERIE
- 2EEMPE
- 1EEPE
- 0EERE
5 fields
| Field | Bits | What it does |
|---|
| EEPM | 5:4 | EEPROM Programming Mode Bits0 Erase and Write in one operation1 Erase Only2 Write Only
|
| EERIE | 3 | EEPROM Ready Interrupt Enable |
| EEMPE | 2 | EEPROM Master Write Enable |
| EEPE | 1 | EEPROM Write Enable |
| EERE | 0 | EEPROM Read Enable |
EEDREEPROM Data Register
- Address
0x40 I/O 0x20
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
EEARLEEPROM Address Register Low Byte
- Address
0x41 I/O 0x21
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
SPI Serial Peripheral Interface
SPCRSPI Control Register
- Address
0x4C I/O 0x2C
- Reset
0x00
- Access
- read/write
- 7SPIE
- 6SPE
- 5DORD
- 4MSTR
- 3CPOL
- 2CPHA
- 1SPR1
- 0SPR0
7 fields
| Field | Bits | What it does |
|---|
| SPIE | 7 | SPI Interrupt Enable |
| SPE | 6 | SPI Enable |
| DORD | 5 | Data Order |
| MSTR | 4 | Master/Slave Select |
| CPOL | 3 | Clock polarity |
| CPHA | 2 | Clock Phase |
| SPR | 1:0 | SPI Clock Rate Selects0 fosc/41 fosc/162 fosc/643 fosc/1284 fosc/25 fosc/86 fosc/327 fosc/64
|
SPSRSPI Status Register
- Address
0x4D I/O 0x2D
- Reset
0x00
- Access
- read/write
- 7SPIF
- 6WCOL
- 5–
- 4–
- 3–
- 2–
- 1–
- 0SPI2X
3 fields
| Field | Bits | What it does |
|---|
| SPIF | 7 | SPI Interrupt Flag |
| WCOL | 6 | Write Collision Flag |
| SPI2X | 0 | Double SPI Speed Bit |
SPDRSPI Data Register
- Address
0x4E I/O 0x2E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
AC Analog Comparator
ACSRAnalog Comparator Control And Status Register
- Address
0x50 I/O 0x30
- Reset
0x00
- Access
- read/write
- 7ACD
- 6ACBG
- 5ACO
- 4ACI
- 3ACIE
- 2ACIC
- 1ACIS1
- 0ACIS0
7 fields
| Field | Bits | What it does |
|---|
| ACD | 7 | Analog Comparator Disable |
| ACBG | 6 | Analog Comparator Bandgap Select |
| ACO | 5 | Analog Compare Output |
| ACI | 4 | Analog Comparator Interrupt Flag |
| ACIE | 3 | Analog Comparator Interrupt Enable |
| ACIC | 2 | Analog Comparator Input Capture Enable |
| ACIS | 1:0 | Analog Comparator Interrupt Mode Select bits0 Interrupt on Toggle1 Reserved2 Interrupt on Falling Edge3 Interrupt on Rising Edge
|
DIDR1Digital Input Disable Register 1
- Address
0x7F
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1AIN1D
- 0AIN0D
2 fields
| Field | Bits | What it does |
|---|
| AIN1D | 1 | AIN1 Digital Input Disable |
| AIN0D | 0 | AIN0 Digital Input Disable |
WDT Watchdog Timer
WDTCSRWatchdog Timer Control Register
- Address
0x60
- Reset
0x00
- Access
- read/write
- 7WDIF
- 6WDIE
- 5WDP5
- 4WDCE
- 3WDE
- 2WDP2
- 1WDP1
- 0WDP0
5 fields
| Field | Bits | What it does |
|---|
| WDIF | 7 | Watchdog Timeout Interrupt Flag |
| WDIE | 6 | Watchdog Timeout Interrupt Enable |
| WDP | 5,2,1,0 | Watchdog Timer Prescaler Bits0 Oscillator Cycles 2K1 Oscillator Cycles 4K2 Oscillator Cycles 8K3 Oscillator Cycles 16K4 Oscillator Cycles 32K5 Oscillator Cycles 64K6 Oscillator Cycles 128K7 Oscillator Cycles 256K8 Oscillator Cycles 512K9 Oscillator Cycles 1024K
|
| WDCE | 4 | Watchdog Change Enable |
| WDE | 3 | Watch Dog Enable |
ADC Analog-to-Digital Converter
ADCADC Data Register Bytes
- Address
0x78
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
ADCSRAThe ADC Control and Status register A
- Address
0x7A
- Reset
0x00
- Access
- read/write
- 7ADEN
- 6ADSC
- 5ADATE
- 4ADIF
- 3ADIE
- 2ADPS2
- 1ADPS1
- 0ADPS0
6 fields
| Field | Bits | What it does |
|---|
| ADEN | 7 | ADC Enable |
| ADSC | 6 | ADC Start Conversion |
| ADATE | 5 | ADC Auto Trigger Enable |
| ADIF | 4 | ADC Interrupt Flag |
| ADIE | 3 | ADC Interrupt Enable |
| ADPS | 2:0 | ADC Prescaler Select Bits0 21 22 43 84 165 326 647 128
|
ADCSRBThe ADC Control and Status register B
- Address
0x7B
- Reset
0x00
- Access
- read/write
- 7–
- 6ACME
- 5–
- 4–
- 3–
- 2ADTS2
- 1ADTS1
- 0ADTS0
2 fields
| Field | Bits | What it does |
|---|
| ACME | 6 | |
| ADTS | 2:0 | ADC Auto Trigger Source bits0 Free Running mode1 Analog Comparator2 External Interrupt Request 03 Timer/Counter0 Compare Match A4 Timer/Counter0 Overflow5 Timer/Counter1 Compare Match B6 Timer/Counter1 Overflow7 Timer/Counter1 Capture Event
|
ADMUXThe ADC multiplexer Selection Register
- Address
0x7C
- Reset
0x00
- Access
- read/write
- 7REFS1
- 6REFS0
- 5ADLAR
- 4–
- 3MUX3
- 2MUX2
- 1MUX1
- 0MUX0
3 fields
| Field | Bits | What it does |
|---|
| REFS | 7:6 | Reference Selection Bits0 AREF, Internal Vref turned off1 AVCC with external capacitor at AREF pin2 Reserved3 Internal 1.1V Voltage Reference with external capacitor at AREF pin
|
| ADLAR | 5 | Left Adjust Result |
| MUX | 3:0 | Analog Channel Selection Bits0 ADC Single Ended Input pin 01 ADC Single Ended Input pin 12 ADC Single Ended Input pin 23 ADC Single Ended Input pin 34 ADC Single Ended Input pin 45 ADC Single Ended Input pin 56 ADC Single Ended Input pin 67 ADC Single Ended Input pin 78 Temperature sensor14 Internal Reference (VBG)15 0V (GND)
|
DIDR0Digital Input Disable Register
- Address
0x7E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5ADC5D
- 4ADC4D
- 3ADC3D
- 2ADC2D
- 1ADC1D
- 0ADC0D
6 fields
| Field | Bits | What it does |
|---|
| ADC5D | 5 | |
| ADC4D | 4 | |
| ADC3D | 3 | |
| ADC2D | 2 | |
| ADC1D | 1 | |
| ADC0D | 0 | |
TWI Two Wire Serial Interface
TWBRTWI Bit Rate register
- Address
0xB8
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TWSRTWI Status Register
- Address
0xB9
- Reset
0x00
- Access
- read/write
- 7TWS4
- 6TWS3
- 5TWS2
- 4TWS1
- 3TWS0
- 2–
- 1TWPS1
- 0TWPS0
2 fields
| Field | Bits | What it does |
|---|
| TWS | 7:3 | TWI Status |
| TWPS | 1:0 | TWI Prescaler |
TWARTWI (Slave) Address register
- Address
0xBA
- Reset
0x00
- Access
- read/write
- 7TWA6
- 6TWA5
- 5TWA4
- 4TWA3
- 3TWA2
- 2TWA1
- 1TWA0
- 0TWGCE
2 fields
| Field | Bits | What it does |
|---|
| TWA | 7:1 | TWI (Slave) Address register Bits |
| TWGCE | 0 | TWI General Call Recognition Enable Bit |
TWDRTWI Data register
- Address
0xBB
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TWCRTWI Control Register
- Address
0xBC
- Reset
0x00
- Access
- read/write
- 7TWINT
- 6TWEA
- 5TWSTA
- 4TWSTO
- 3TWWC
- 2TWEN
- 1–
- 0TWIE
7 fields
| Field | Bits | What it does |
|---|
| TWINT | 7 | TWI Interrupt Flag |
| TWEA | 6 | TWI Enable Acknowledge Bit |
| TWSTA | 5 | TWI Start Condition Bit |
| TWSTO | 4 | TWI Stop Condition Bit |
| TWWC | 3 | TWI Write Collision Flag |
| TWEN | 2 | TWI Enable Bit |
| TWIE | 0 | TWI Interrupt Enable |
TWAMRTWI (Slave) Address Mask Register
- Address
0xBD
- Reset
0x00
- Access
- read/write
- 7TWAM6
- 6TWAM5
- 5TWAM4
- 4TWAM3
- 3TWAM2
- 2TWAM1
- 1TWAM0
- 0–
1 field
| Field | Bits | What it does |
|---|
| TWAM | 7:1 | |
USART0 USART
UCSR0AUSART Control and Status Register A
- Address
0xC0
- Reset
0x00
- Access
- read/write
- 7RXC0
- 6TXC0
- 5UDRE0
- 4FE0
- 3DOR0
- 2UPE0
- 1U2X0
- 0MPCM0
8 fields
| Field | Bits | What it does |
|---|
| RXC0 | 7 | USART Receive Complete |
| TXC0 | 6 | USART Transmit Complete |
| UDRE0 | 5 | USART Data Register Empty |
| FE0 | 4 | Framing Error |
| DOR0 | 3 | Data overRun |
| UPE0 | 2 | Parity Error |
| U2X0 | 1 | Double the USART transmission speed |
| MPCM0 | 0 | Multi-processor Communication Mode |
UCSR0BUSART Control and Status Register B
- Address
0xC1
- Reset
0x00
- Access
- read/write
- 7RXCIE0
- 6TXCIE0
- 5UDRIE0
- 4RXEN0
- 3TXEN0
- 2UCSZ02
- 1RXB80
- 0TXB80
8 fields
| Field | Bits | What it does |
|---|
| RXCIE0 | 7 | RX Complete Interrupt Enable |
| TXCIE0 | 6 | TX Complete Interrupt Enable |
| UDRIE0 | 5 | USART Data register Empty Interrupt Enable |
| RXEN0 | 4 | Receiver Enable |
| TXEN0 | 3 | Transmitter Enable |
| UCSZ02 | 2 | Character Size - together with UCSZ0 in UCSR0C |
| RXB80 | 1 | Receive Data Bit 8 |
| TXB80 | 0 | Transmit Data Bit 8 |
UCSR0CUSART Control and Status Register C
- Address
0xC2
- Reset
0x00
- Access
- read/write
- 7UMSEL01
- 6UMSEL00
- 5UPM01
- 4UPM00
- 3USBS0
- 2UCSZ01
- 1UCSZ00
- 0UCPOL0
5 fields
| Field | Bits | What it does |
|---|
| UMSEL0 | 7:6 | USART Mode Select0 Asynchronous USART1 Synchronous USART3 Master SPI
|
| UPM0 | 5:4 | Parity Mode Bits0 Disabled1 Reserved2 Enabled, Even Parity3 Enabled, Odd Parity
|
| USBS0 | 3 | Stop Bit Select |
| UCSZ0 | 2:1 | Character Size - together with UCSZ2 in UCSR0B |
| UCPOL0 | 0 | Clock Polarity |
UBRR0USART Baud Rate Register Bytes
- Address
0xC4
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
UDR0USART I/O Data Register
- Address
0xC6
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–