ATSAME70Q20B SPI0 registers

The 14 registers of SPI0 (Serial Peripheral Interface), from 0x40008000, with their reset value and every field. The ATSAME70Q20B has 2961 registers in 67 peripherals, one page each.

SPI0 Serial Peripheral Interface

SPI_CRControl Register

Address
0x40008000
Reset
0x00000000
Access
write only
Size
32-bit
5 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
REQCLR12Request to Clear the Comparison Trigger
SWRST7SPI Software Reset
SPIDIS1SPI Disable
SPIEN0SPI Enable

SPI_MRMode Register

Address
0x40008004
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
PCS19:16Peripheral Chip Select
  • 7 NPCS3 as Chip Select
  • 11 NPCS2 as Chip Select
  • 13 NPCS1 as Chip Select
  • 14 NPCS0 as Chip Select
LLB7Local Loopback Enable
WDRBT5Wait Data Read Before Transfer
MODFDIS4Mode Fault Detection
PCSDEC2Chip Select Decode
PS1Peripheral Select
MSTR0Master/Slave Mode
  • 0 Slave
  • 1 Master
DLYBCS31:24Delay Between Chip Selects

SPI_RDRReceive Data Register

Address
0x40008008
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
PCS19:16Peripheral Chip Select
RD15:0Receive Data

SPI_TDRTransmit Data Register

Address
0x4000800C
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
PCS19:16Peripheral Chip Select
  • 7 NPCS3 as Chip Select
  • 11 NPCS2 as Chip Select
  • 13 NPCS1 as Chip Select
  • 14 NPCS0 as Chip Select
TD15:0Transmit Data

SPI_SRStatus Register

Address
0x40008010
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
SPIENS16SPI Enable Status
UNDES10Underrun Error Status (Slave mode only) (cleared on read)
TXEMPTY9Transmission Registers Empty (cleared by writing SPI_TDR)
NSSR8NSS Rising (cleared on read)
OVRES3Overrun Error Status (cleared on read)
MODF2Mode Fault Error (cleared on read)
TDRE1Transmit Data Register Empty (cleared by writing SPI_TDR)
RDRF0Receive Data Register Full (cleared by reading SPI_RDR)

SPI_IERInterrupt Enable Register

Address
0x40008014
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
UNDES10Underrun Error Interrupt Enable
TXEMPTY9Transmission Registers Empty Enable
NSSR8NSS Rising Interrupt Enable
OVRES3Overrun Error Interrupt Enable
MODF2Mode Fault Error Interrupt Enable
TDRE1SPI Transmit Data Register Empty Interrupt Enable
RDRF0Receive Data Register Full Interrupt Enable

SPI_IDRInterrupt Disable Register

Address
0x40008018
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
UNDES10Underrun Error Interrupt Disable
TXEMPTY9Transmission Registers Empty Disable
NSSR8NSS Rising Interrupt Disable
OVRES3Overrun Error Interrupt Disable
MODF2Mode Fault Error Interrupt Disable
TDRE1SPI Transmit Data Register Empty Interrupt Disable
RDRF0Receive Data Register Full Interrupt Disable

SPI_IMRInterrupt Mask Register

Address
0x4000801C
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
UNDES10Underrun Error Interrupt Mask
TXEMPTY9Transmission Registers Empty Mask
NSSR8NSS Rising Interrupt Mask
OVRES3Overrun Error Interrupt Mask
MODF2Mode Fault Error Interrupt Mask
TDRE1SPI Transmit Data Register Empty Interrupt Mask
RDRF0Receive Data Register Full Interrupt Mask

SPI_CSR0Chip Select Register

Address
0x40008030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SPCK
SCBR15:8Serial Clock Bit Rate
BITS7:4Bits Per Transfer
  • 0 8 bits for transfer
  • 1 9 bits for transfer
  • 2 10 bits for transfer
  • 3 11 bits for transfer
  • 4 12 bits for transfer
  • 5 13 bits for transfer
  • 6 14 bits for transfer
  • 7 15 bits for transfer
  • 8 16 bits for transfer
CSAAT3Chip Select Active After Transfer
CSNAAT2Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA1Clock Phase
  • 0 Data is valid on clock trailing edge (NCPHA=0)
  • 1 Data is valid on clock leading edge (NCPHA=1)
CPOL0Clock Polarity
  • 0 Clock is low when inactive (CPOL=0)
  • 1 Clock is high when inactive (CPOL=1)
DLYBCT31:24Delay Between Consecutive Transfers

SPI_CSR1Chip Select Register

Address
0x40008034
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SPCK
SCBR15:8Serial Clock Bit Rate
BITS7:4Bits Per Transfer
  • 0 8 bits for transfer
  • 1 9 bits for transfer
  • 2 10 bits for transfer
  • 3 11 bits for transfer
  • 4 12 bits for transfer
  • 5 13 bits for transfer
  • 6 14 bits for transfer
  • 7 15 bits for transfer
  • 8 16 bits for transfer
CSAAT3Chip Select Active After Transfer
CSNAAT2Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA1Clock Phase
  • 0 Data is valid on clock trailing edge (NCPHA=0)
  • 1 Data is valid on clock leading edge (NCPHA=1)
CPOL0Clock Polarity
  • 0 Clock is low when inactive (CPOL=0)
  • 1 Clock is high when inactive (CPOL=1)
DLYBCT31:24Delay Between Consecutive Transfers

SPI_CSR2Chip Select Register

Address
0x40008038
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SPCK
SCBR15:8Serial Clock Bit Rate
BITS7:4Bits Per Transfer
  • 0 8 bits for transfer
  • 1 9 bits for transfer
  • 2 10 bits for transfer
  • 3 11 bits for transfer
  • 4 12 bits for transfer
  • 5 13 bits for transfer
  • 6 14 bits for transfer
  • 7 15 bits for transfer
  • 8 16 bits for transfer
CSAAT3Chip Select Active After Transfer
CSNAAT2Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA1Clock Phase
  • 0 Data is valid on clock trailing edge (NCPHA=0)
  • 1 Data is valid on clock leading edge (NCPHA=1)
CPOL0Clock Polarity
  • 0 Clock is low when inactive (CPOL=0)
  • 1 Clock is high when inactive (CPOL=1)
DLYBCT31:24Delay Between Consecutive Transfers

SPI_CSR3Chip Select Register

Address
0x4000803C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SPCK
SCBR15:8Serial Clock Bit Rate
BITS7:4Bits Per Transfer
  • 0 8 bits for transfer
  • 1 9 bits for transfer
  • 2 10 bits for transfer
  • 3 11 bits for transfer
  • 4 12 bits for transfer
  • 5 13 bits for transfer
  • 6 14 bits for transfer
  • 7 15 bits for transfer
  • 8 16 bits for transfer
CSAAT3Chip Select Active After Transfer
CSNAAT2Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA1Clock Phase
  • 0 Data is valid on clock trailing edge (NCPHA=0)
  • 1 Data is valid on clock leading edge (NCPHA=1)
CPOL0Clock Polarity
  • 0 Clock is low when inactive (CPOL=0)
  • 1 Clock is high when inactive (CPOL=1)
DLYBCT31:24Delay Between Consecutive Transfers

SPI_WPMRWrite Protection Mode Register

Address
0x400080E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5460041 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

SPI_WPSRWrite Protection Status Register

Address
0x400080E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC15:8Write Protection Violation Source
WPVS0Write Protection Violation Status