ATSAME70Q20B SSC registers

The 18 registers of SSC (Synchronous Serial Controller), from 0x40004000, with their reset value and every field. The ATSAME70Q20B has 2961 registers in 67 peripherals, one page each.

SSC Synchronous Serial Controller

SSC_CRControl Register

Address
0x40004000
Reset
0x00000000
Access
write only
Size
32-bit
5 fields
FieldBitsWhat it does
SWRST15Software Reset
TXDIS9Transmit Disable
TXEN8Transmit Enable
RXDIS1Receive Disable
RXEN0Receive Enable

SSC_CMRClock Mode Register

Address
0x40004004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DIV11:0Clock Divider

SSC_RCMRReceive Clock Mode Register

Address
0x40004010
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
STTDLY23:16Receive Start Delay
STOP12Receive Stop Selection
START11:8Receive Start Selection
  • 0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
  • 1 Transmit start
  • 2 Detection of a low level on RF signal
  • 3 Detection of a high level on RF signal
  • 4 Detection of a falling edge on RF signal
  • 5 Detection of a rising edge on RF signal
  • 6 Detection of any level change on RF signal
  • 7 Detection of any edge on RF signal
  • 8 Compare 0
CKG7:6Receive Clock Gating Selection
  • 0 None
  • 1 Receive Clock enabled only if RF Low
  • 2 Receive Clock enabled only if RF High
CKI5Receive Clock Inversion
CKO4:2Receive Clock Output Mode Selection
  • 0 None, RK pin is an input
  • 1 Continuous Receive Clock, RK pin is an output
  • 2 Receive Clock only during data transfers, RK pin is an output
CKS1:0Receive Clock Selection
  • 0 Divided Clock
  • 1 TK Clock signal
  • 2 RK pin
PERIOD31:24Receive Period Divider Selection

SSC_RFMRReceive Frame Mode Register

Address
0x40004014
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
FSEDGE24Frame Sync Edge Detection
  • 0 Positive Edge Detection
  • 1 Negative Edge Detection
FSOS22:20Receive Frame Sync Output Selection
  • 0 None, RF pin is an input
  • 1 Negative Pulse, RF pin is an output
  • 2 Positive Pulse, RF pin is an output
  • 3 Driven Low during data transfer, RF pin is an output
  • 4 Driven High during data transfer, RF pin is an output
  • 5 Toggling at each start of data transfer, RF pin is an output
FSLEN19:16Receive Frame Sync Length
DATNB11:8Data Number per Frame
MSBF7Most Significant Bit First
LOOP5Loop Mode
DATLEN4:0Data Length
FSLEN_EXT31:28FSLEN Field Extension

SSC_TCMRTransmit Clock Mode Register

Address
0x40004018
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
STTDLY23:16Transmit Start Delay
START11:8Transmit Start Selection
  • 0 Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data
  • 1 Receive start
  • 2 Detection of a low level on TF signal
  • 3 Detection of a high level on TF signal
  • 4 Detection of a falling edge on TF signal
  • 5 Detection of a rising edge on TF signal
  • 6 Detection of any level change on TF signal
  • 7 Detection of any edge on TF signal
CKG7:6Transmit Clock Gating Selection
  • 0 None
  • 1 Transmit Clock enabled only if TF Low
  • 2 Transmit Clock enabled only if TF High
CKI5Transmit Clock Inversion
CKO4:2Transmit Clock Output Mode Selection
  • 0 None, TK pin is an input
  • 1 Continuous Transmit Clock, TK pin is an output
  • 2 Transmit Clock only during data transfers, TK pin is an output
CKS1:0Transmit Clock Selection
  • 0 Divided Clock
  • 1 RK Clock signal
  • 2 TK pin
PERIOD31:24Transmit Period Divider Selection

SSC_TFMRTransmit Frame Mode Register

Address
0x4000401C
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FSEDGE24Frame Sync Edge Detection
  • 0 Positive Edge Detection
  • 1 Negative Edge Detection
FSDEN23Frame Sync Data Enable
FSOS22:20Transmit Frame Sync Output Selection
  • 0 None, TF pin is an input
  • 1 Negative Pulse, TF pin is an output
  • 2 Positive Pulse, TF pin is an output
  • 3 Driven Low during data transfer
  • 4 Driven High during data transfer
  • 5 Toggling at each start of data transfer
FSLEN19:16Transmit Frame Sync Length
DATNB11:8Data Number per Frame
MSBF7Most Significant Bit First
DATDEF5Data Default Value
DATLEN4:0Data Length
FSLEN_EXT31:28FSLEN Field Extension

SSC_RHRReceive Holding Register

Address
0x40004020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RDAT31:0Receive Data

SSC_THRTransmit Holding Register

Address
0x40004024
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
TDAT31:0Transmit Data

SSC_RSHRReceive Sync. Holding Register

Address
0x40004030
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RSDAT15:0Receive Synchronization Data

SSC_TSHRTransmit Sync. Holding Register

Address
0x40004034
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TSDAT15:0Transmit Synchronization Data

SSC_RC0RReceive Compare 0 Register

Address
0x40004038
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CP015:0Receive Compare Data 0

SSC_RC1RReceive Compare 1 Register

Address
0x4000403C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CP115:0Receive Compare Data 1

SSC_SRStatus Register

Address
0x40004040
Reset
0x00000000
Access
read only
Size
32-bit
10 fields
FieldBitsWhat it does
RXEN17Receive Enable
TXEN16Transmit Enable
RXSYN11Receive Sync
TXSYN10Transmit Sync
CP19Compare 1
CP08Compare 0
OVRUN5Receive Overrun
RXRDY4Receive Ready
TXEMPTY1Transmit Empty
TXRDY0Transmit Ready

SSC_IERInterrupt Enable Register

Address
0x40004044
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
FieldBitsWhat it does
RXSYN11Rx Sync Interrupt Enable
TXSYN10Tx Sync Interrupt Enable
CP19Compare 1 Interrupt Enable
CP08Compare 0 Interrupt Enable
OVRUN5Receive Overrun Interrupt Enable
RXRDY4Receive Ready Interrupt Enable
TXEMPTY1Transmit Empty Interrupt Enable
TXRDY0Transmit Ready Interrupt Enable

SSC_IDRInterrupt Disable Register

Address
0x40004048
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
FieldBitsWhat it does
RXSYN11Rx Sync Interrupt Enable
TXSYN10Tx Sync Interrupt Enable
CP19Compare 1 Interrupt Disable
CP08Compare 0 Interrupt Disable
OVRUN5Receive Overrun Interrupt Disable
RXRDY4Receive Ready Interrupt Disable
TXEMPTY1Transmit Empty Interrupt Disable
TXRDY0Transmit Ready Interrupt Disable

SSC_IMRInterrupt Mask Register

Address
0x4000404C
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
RXSYN11Rx Sync Interrupt Mask
TXSYN10Tx Sync Interrupt Mask
CP19Compare 1 Interrupt Mask
CP08Compare 0 Interrupt Mask
OVRUN5Receive Overrun Interrupt Mask
RXRDY4Receive Ready Interrupt Mask
TXEMPTY1Transmit Empty Interrupt Mask
TXRDY0Transmit Ready Interrupt Mask

SSC_WPMRWrite Protection Mode Register

Address
0x400040E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5460803 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

SSC_WPSRWrite Protection Status Register

Address
0x400040E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC23:8Write Protect Violation Source
WPVS0Write Protection Violation Status