ATSAML21E16B MCLK registers

The 13 registers of MCLK (Main Clock), from 0x40000400, with their reset value and every field. The ATSAML21E16B has 1205 registers in 40 peripherals, one page each.

MCLK Main Clock

CTRLAControl A

Address
0x40000400
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

INTENCLRInterrupt Enable Clear

Address
0x40000401
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0CKRDY
1 field
FieldBitsWhat it does
CKRDY0Clock Ready Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x40000402
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0CKRDY
1 field
FieldBitsWhat it does
CKRDY0Clock Ready Interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x40000403
Reset
0x01
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0CKRDY
1 field
FieldBitsWhat it does
CKRDY0Clock Ready

CPUDIVCPU Clock Division

Address
0x40000404
Reset
0x01
Access
read/write
  1. 7CPUDIV7
  2. 6CPUDIV6
  3. 5CPUDIV5
  4. 4CPUDIV4
  5. 3CPUDIV3
  6. 2CPUDIV2
  7. 1CPUDIV1
  8. 0CPUDIV0
1 field
FieldBitsWhat it does
CPUDIV7:0CPU Clock Division Factor
  • 1 Divide by 1
  • 2 Divide by 2
  • 4 Divide by 4
  • 8 Divide by 8
  • 16 Divide by 16
  • 32 Divide by 32
  • 64 Divide by 64
  • 128 Divide by 128

LPDIVLow-Power Clock Division

Address
0x40000405
Reset
0x01
Access
read/write
  1. 7LPDIV7
  2. 6LPDIV6
  3. 5LPDIV5
  4. 4LPDIV4
  5. 3LPDIV3
  6. 2LPDIV2
  7. 1LPDIV1
  8. 0LPDIV0
1 field
FieldBitsWhat it does
LPDIV7:0Low-Power Clock Division Factor
  • 1 Divide by 1
  • 2 Divide by 2
  • 4 Divide by 4
  • 8 Divide by 8
  • 16 Divide by 16
  • 32 Divide by 32
  • 64 Divide by 64
  • 128 Divide by 128

BUPDIVBackup Clock Division

Address
0x40000406
Reset
0x01
Access
read/write
  1. 7BUPDIV7
  2. 6BUPDIV6
  3. 5BUPDIV5
  4. 4BUPDIV4
  5. 3BUPDIV3
  6. 2BUPDIV2
  7. 1BUPDIV1
  8. 0BUPDIV0
1 field
FieldBitsWhat it does
BUPDIV7:0Backup Clock Division Factor
  • 1 Divide by 1
  • 2 Divide by 2
  • 4 Divide by 4
  • 8 Divide by 8
  • 16 Divide by 16
  • 32 Divide by 32
  • 64 Divide by 64
  • 128 Divide by 128

AHBMASKAHB Mask

Address
0x40000410
Reset
0x000FFFFF
Access
read/write
Size
32-bit
17 fields
FieldBitsWhat it does
HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_19HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask
HSRAM_AHBSETUPKEEPER_18HSRAM_AHBSETUPKEEPER AHB Clock Mask
H2LBRIDGES_H_17H2LBRIDGES_H AHB Clock Mask
L2HBRIDGES_H_16L2HBRIDGES_H AHB Clock Mask
NVMCTRL_PICACHU_15NVMCTRL_PICACHU AHB Clock Mask
PAC_14PAC AHB Clock Mask
USB_12USB AHB Clock Mask
DMAC_11DMAC AHB Clock Mask
LPRAM_10LPRAM AHB Clock Mask
HSRAM_9HSRAM AHB Clock Mask
NVMCTRL_8NVMCTRL AHB Clock Mask
DSU_5DSU AHB Clock Mask
HPB4_4HPB4 AHB Clock Mask
HPB3_3HPB3 AHB Clock Mask
HPB2_2HPB2 AHB Clock Mask
HPB1_1HPB1 AHB Clock Mask
HPB0_0HPB0 AHB Clock Mask

APBAMASKAPBA Mask

Address
0x40000414
Reset
0x00001FFF
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
PORT_10PORT APB Clock Enable
EIC_9EIC APB Clock Enable
RTC_8RTC APB Clock Enable
WDT_7WDT APB Clock Enable
GCLK_6GCLK APB Clock Enable
SUPC_5SUPC APB Clock Enable
OSC32KCTRL_4OSC32KCTRL APB Clock Enable
OSCCTRL_3OSCCTRL APB Clock Enable
RSTC_2RSTC APB Clock Enable
MCLK_1MCLK APB Clock Enable
PM_0PM APB Clock Enable

APBBMASKAPBB Mask

Address
0x40000418
Reset
0x00000017
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
NVMCTRL_2NVMCTRL APB Clock Enable
DSU_1DSU APB Clock Enable
USB_0USB APB Clock Enable

APBCMASKAPBC Mask

Address
0x4000041C
Reset
0x00007FFF
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
TRNG_14TRNG APB Clock Enable
AES_13AES APB Clock Enable
DAC_12DAC APB Clock Enable
TC1_9TC1 APB Clock Enable
TC0_8TC0 APB Clock Enable
TCC2_7TCC2 APB Clock Enable
TCC1_6TCC1 APB Clock Enable
TCC0_5TCC0 APB Clock Enable
SERCOM4_4SERCOM4 APB Clock Enable
SERCOM3_3SERCOM3 APB Clock Enable
SERCOM2_2SERCOM2 APB Clock Enable
SERCOM1_1SERCOM1 APB Clock Enable
SERCOM0_0SERCOM0 APB Clock Enable

APBDMASKAPBD Mask

Address
0x40000420
Reset
0x000000FF
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CCL_7CCL APB Clock Enable
OPAMP_6OPAMP APB Clock Enable
PTC_5PTC APB Clock Enable
AC_4AC APB Clock Enable
ADC_3ADC APB Clock Enable
TC4_2TC4 APB Clock Enable
SERCOM5_1SERCOM5 APB Clock Enable
EVSYS_0EVSYS APB Clock Enable

APBEMASKAPBE Mask

Address
0x40000424
Reset
0x0000000D
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PAC_0PAC APB Clock Enable