ATSAML21E16B PM registers

The 8 registers of PM (Power Manager), from 0x40000000, with their reset value and every field. The ATSAML21E16B has 1205 registers in 40 peripherals, one page each.

PM Power Manager

CTRLAControl A

Address
0x40000000
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2IORET
  7. 1–
  8. 0–
1 field
FieldBitsWhat it does
IORET2I/O Retention

SLEEPCFGSleep Configuration

Address
0x40000001
Reset
0x02
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2SLEEPMODE2
  7. 1SLEEPMODE1
  8. 0SLEEPMODE0
1 field
FieldBitsWhat it does
SLEEPMODE2:0Sleep Mode
  • 2 CPU, AHBx, and APBx clocks are OFF
  • 4 All Clocks are OFF
  • 5 Only Backup domain is powered ON
  • 6 All power domains are powered OFF

PLCFGPerformance Level Configuration

Address
0x40000002
Reset
0x00
Access
read/write
  1. 7PLDIS
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1PLSEL1
  8. 0PLSEL0
2 fields
FieldBitsWhat it does
PLDIS7Performance Level Disable
PLSEL1:0Performance Level Select
  • 0 Performance Level 0
  • 1 Performance Level 1
  • 2 Performance Level 2

INTENCLRInterrupt Enable Clear

Address
0x40000004
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PLRDY
1 field
FieldBitsWhat it does
PLRDY0Performance Level Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x40000005
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PLRDY
1 field
FieldBitsWhat it does
PLRDY0Performance Level Ready interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x40000006
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PLRDY
1 field
FieldBitsWhat it does
PLRDY0Performance Level Ready

STDBYCFGStandby Configuration

Address
0x40000008
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
FieldBitsWhat it does
BBIASPP15:14Back Bias for PicoPram
BBIASLP13:12Back Bias for HMCRAMCLP
BBIASHS11:10Back Bias for HMCRAMCHS
LINKPD9:8Linked Power Domain
  • 0 Power domains are not linked
  • 1 PD0 and PD1 power domains are linked
  • 2 PD1 and PD2 power domains are linked
  • 3 All power domains are linked
VREGSMOD7:6Voltage Regulator Standby mode
  • 0 Automatic mode
  • 1 Performance oriented
  • 2 Low Power oriented
DPGPD15Dynamic Power Gating for PD1
DPGPD04Dynamic Power Gating for PD0
PDCFG1:0Power Domain Configuration
  • 0 All power domains switching is handled by hardware.
  • 1 PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware.
  • 2 PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware.
  • 3 All power domains are forced ACTIVE.

PWSAKDLYPower Switch Acknowledge Delay

Address
0x4000000C
Reset
0x00
Access
read/write
  1. 7IGNACK
  2. 6DLYVAL6
  3. 5DLYVAL5
  4. 4DLYVAL4
  5. 3DLYVAL3
  6. 2DLYVAL2
  7. 1DLYVAL1
  8. 0DLYVAL0
2 fields
FieldBitsWhat it does
IGNACK7Ignore Acknowledge
DLYVAL6:0Delay Value