ATSAMRH71F20C HSDRAMC registers

The 11 registers of HSDRAMC (Hardened SDRAM Controller), from 0x40082000, with their reset value and every field. The ATSAMRH71F20C has 3366 registers in 56 peripherals, one page each.

HSDRAMC Hardened SDRAM Controller

HSDRAMC_MRMode Register

Address
0x40082000
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MODE2:0SDRAMC Command Mode
  • 0 Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM.
  • 1 The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
  • 2 The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
  • 3 The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
  • 4 The SDRAMC issues an "Autorefresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the SDRAM.
  • 5 The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power

HSDRAMC_TRRefresh Timer Register

Address
0x40082004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
COUNT11:0SDRAMC Refresh Timer Count

HSDRAMC_CRConfiguration Register

Address
0x40082008
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
RMW9Read Modify Write
DBW8Data Bus Width
CAS7:6CAS Latency
  • 1 1 cycle latency
  • 2 2 cycle latency
  • 3 3 cycle latency
NB5Number of Banks
  • 0 2 banks
  • 1 4 banks
NR4:3Number of Row Bits
  • 0 11 bits to define the row number, up to 2048 rows
  • 1 12 bits to define the row number, up to 4096 rows
  • 2 13 bits to define the row number, up to 8192 rows
NC2:0Number of Column Bits
  • 0 8 bits to define the column number, up to 256 columns
  • 1 9 bits to define the column number, up to 512 columns
  • 2 10 bits to define the column number, up to 1024 columns
  • 3 11 bits to define the column number, up to 2048 columns
  • 4 12 bits to define the column number, up to 4096 columns

HSDRAMC_SDRSetup Delay Register

Address
0x4008200C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
TXSR23:20Exit Self-Refresh to Active Delay
TRAS19:16Active to Precharge Delay
TRCD15:12Row to Column Delay
TRP11:8Row Precharge Delay
TRC_TRFC7:4Row Cycle Delay and Row Refresh Cycle
TWR3:0Write Recovery Delay

HSDRAMC_IERInterrupt Enable Register

Address
0x40082014
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
RES0Refresh Error Interrupt Enable

HSDRAMC_IDRInterrupt Disable Register

Address
0x40082018
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
RES0Refresh Error Interrupt Disable

HSDRAMC_IMRInterrupt Mask Register

Address
0x4008201C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RES0Refresh Error Interrupt Mask

HSDRAMC_ISRInterrupt Status Register

Address
0x40082020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RES0Refresh Error Status (cleared on read)

HSDRAMC_CFR1Configuration Register 1

Address
0x40082024
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
UNAL8Support Unaligned Access
  • 0 Unaligned access is not supported.
  • 1 Unaligned access is supported.
TMRD3:0Load Mode Register Command to Active or Refresh Command

HSDRAMC_WPMRWrite Protection Mode Register

Address
0x40082028
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5456978 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

HSDRAMC_WPSRWrite Protection Status Register

Address
0x4008202C
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC15:8Write Protection Violation Source
WPVS0Write Protection Violation Status