ATSAMRH71F20C HSMC registers

The 26 registers of HSMC (Harden Static Memory Controller), from 0x40081000, with their reset value and every field. The ATSAMRH71F20C has 3366 registers in 56 peripherals, one page each.

HSMC Harden Static Memory Controller

HSMC_CS0.HSMC_SETUPHSMC Setup Register

Address
0x40081000
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

HSMC_CS0.HSMC_PULSEHSMC Pulse Register

Address
0x40081004
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

HSMC_CS0.HSMC_CYCLEHSMC Cycle Register

Address
0x40081008
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

HSMC_CS0.HSMC_MODEHSMC Mode Register

Address
0x4008100C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
DBW9:8Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
  • 2 32-bit Data Bus
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
RMW_ENABLE2Read-Modify Write enable
WRITE_MODE1Write Mode
READ_MODE0Read Mode

HSMC_CS1.HSMC_SETUPHSMC Setup Register

Address
0x40081010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

HSMC_CS1.HSMC_PULSEHSMC Pulse Register

Address
0x40081014
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

HSMC_CS1.HSMC_CYCLEHSMC Cycle Register

Address
0x40081018
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

HSMC_CS1.HSMC_MODEHSMC Mode Register

Address
0x4008101C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
DBW9:8Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
  • 2 32-bit Data Bus
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
RMW_ENABLE2Read-Modify Write enable
WRITE_MODE1Write Mode
READ_MODE0Read Mode

HSMC_CS2.HSMC_SETUPHSMC Setup Register

Address
0x40081020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

HSMC_CS2.HSMC_PULSEHSMC Pulse Register

Address
0x40081024
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

HSMC_CS2.HSMC_CYCLEHSMC Cycle Register

Address
0x40081028
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

HSMC_CS2.HSMC_MODEHSMC Mode Register

Address
0x4008102C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
DBW9:8Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
  • 2 32-bit Data Bus
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
RMW_ENABLE2Read-Modify Write enable
WRITE_MODE1Write Mode
READ_MODE0Read Mode

HSMC_CS3.HSMC_SETUPHSMC Setup Register

Address
0x40081030
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

HSMC_CS3.HSMC_PULSEHSMC Pulse Register

Address
0x40081034
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

HSMC_CS3.HSMC_CYCLEHSMC Cycle Register

Address
0x40081038
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

HSMC_CS3.HSMC_MODEHSMC Mode Register

Address
0x4008103C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
DBW9:8Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
  • 2 32-bit Data Bus
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
RMW_ENABLE2Read-Modify Write enable
WRITE_MODE1Write Mode
READ_MODE0Read Mode

HSMC_CS4.HSMC_SETUPHSMC Setup Register

Address
0x40081040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

HSMC_CS4.HSMC_PULSEHSMC Pulse Register

Address
0x40081044
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

HSMC_CS4.HSMC_CYCLEHSMC Cycle Register

Address
0x40081048
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

HSMC_CS4.HSMC_MODEHSMC Mode Register

Address
0x4008104C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
DBW9:8Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
  • 2 32-bit Data Bus
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
RMW_ENABLE2Read-Modify Write enable
WRITE_MODE1Write Mode
READ_MODE0Read Mode

HSMC_CS5.HSMC_SETUPHSMC Setup Register

Address
0x40081050
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

HSMC_CS5.HSMC_PULSEHSMC Pulse Register

Address
0x40081054
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

HSMC_CS5.HSMC_CYCLEHSMC Cycle Register

Address
0x40081058
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

HSMC_CS5.HSMC_MODEHSMC Mode Register

Address
0x4008105C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
DBW9:8Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
  • 2 32-bit Data Bus
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
RMW_ENABLE2Read-Modify Write enable
WRITE_MODE1Write Mode
READ_MODE0Read Mode

HSMC_WPMRHSMC Write Protection Mode Register

Address
0x40081070
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protect Enable
WPKEY31:8Write Protection Key
  • 5459267 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

HSMC_WPSRHSMC Write Protection Status Register

Address
0x40081074
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC23:8Write Protection Violation Source
WPVS0Write Protection Violation Status