ATtiny2313 registers
All 54 registers by peripheral, at their data-space address (the I/O address IN and OUT use is shown beside it), with their reset value and every bit.
AC Analog Comparator
DIDRDigital Input Disable Register 1
- Address
0x21 I/O 0x01
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
ACSRAnalog Comparator Control And Status Register
- Address
0x28 I/O 0x08
- Reset
0x00
- Access
- read/write
- 7ACD
- 6ACBG
- 5ACO
- 4ACI
- 3ACIE
- 2ACIC
- 1ACIS1
- 0ACIS0
7 fields
| Field | Bits | What it does |
|---|
| ACD | 7 | Analog Comparator Disable |
| ACBG | 6 | Analog Comparator Bandgap Select |
| ACO | 5 | Analog Compare Output |
| ACI | 4 | Analog Comparator Interrupt Flag |
| ACIE | 3 | Analog Comparator Interrupt Enable |
| ACIC | 2 | |
| ACIS | 1:0 | Analog Comparator Interrupt Mode Select bits0 Interrupt on Toggle1 Reserved2 Interrupt on Falling Edge3 Interrupt on Rising Edge
|
USART USART
UBRRHUSART Baud Rate Register High Byte
- Address
0x22 I/O 0x02
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
UCSRCUSART Control and Status Register C
- Address
0x23 I/O 0x03
- Reset
0x00
- Access
- read/write
- 7–
- 6UMSEL
- 5UPM1
- 4UPM0
- 3USBS
- 2UCSZ1
- 1UCSZ0
- 0UCPOL
5 fields
| Field | Bits | What it does |
|---|
| UMSEL | 6 | USART Mode Select0 Asynchronous Operation1 Synchronous Operation
|
| UPM | 5:4 | Parity Mode Bits0 Disabled1 Reserved2 Enabled, Even Parity3 Enabled, Odd Parity
|
| USBS | 3 | Stop Bit Select |
| UCSZ | 2:1 | Character Size Bits |
| UCPOL | 0 | Clock Polarity |
UBRRLUSART Baud Rate Register Low Byte
- Address
0x29 I/O 0x09
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
UCSRBUSART Control and Status Register B
- Address
0x2A I/O 0x0A
- Reset
0x00
- Access
- read/write
- 7RXCIE
- 6TXCIE
- 5UDRIE
- 4RXEN
- 3TXEN
- 2UCSZ2
- 1RXB8
- 0TXB8
8 fields
| Field | Bits | What it does |
|---|
| RXCIE | 7 | RX Complete Interrupt Enable |
| TXCIE | 6 | TX Complete Interrupt Enable |
| UDRIE | 5 | USART Data register Empty Interrupt Enable |
| RXEN | 4 | Receiver Enable |
| TXEN | 3 | Transmitter Enable |
| UCSZ2 | 2 | Character Size |
| RXB8 | 1 | Receive Data Bit 8 |
| TXB8 | 0 | Transmit Data Bit 8 |
UCSRAUSART Control and Status Register A
- Address
0x2B I/O 0x0B
- Reset
0x00
- Access
- read/write
- 7RXC
- 6TXC
- 5UDRE
- 4FE
- 3DOR
- 2UPE
- 1U2X
- 0MPCM
8 fields
| Field | Bits | What it does |
|---|
| RXC | 7 | USART Receive Complete |
| TXC | 6 | USART Transmit Complete |
| UDRE | 5 | USART Data Register Empty |
| FE | 4 | Framing Error |
| DOR | 3 | Data Overrun |
| UPE | 2 | USART Parity Error |
| U2X | 1 | Double the USART Transmission Speed |
| MPCM | 0 | Multi-processor Communication Mode |
UDRUSART I/O Data Register
- Address
0x2C I/O 0x0C
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
USI Universal Serial Interface
USICRUSI Control Register
- Address
0x2D I/O 0x0D
- Reset
0x00
- Access
- read/write
- 7USISIE
- 6USIOIE
- 5USIWM1
- 4USIWM0
- 3USICS1
- 2USICS0
- 1USICLK
- 0USITC
6 fields
| Field | Bits | What it does |
|---|
| USISIE | 7 | Start Condition Interrupt Enable |
| USIOIE | 6 | Counter Overflow Interrupt Enable |
| USIWM | 5:4 | USI Wire Mode Bits0 Normal Operation1 Three-Wire Mode2 Two-Wire Mode3 Two-Wire Mode Held Low
|
| USICS | 3:2 | USI Clock Source Select Bits |
| USICLK | 1 | Clock Strobe |
| USITC | 0 | Toggle Clock Port Pin |
USISRUSI Status Register
- Address
0x2E I/O 0x0E
- Reset
0x00
- Access
- read/write
- 7USISIF
- 6USIOIF
- 5USIPF
- 4USIDC
- 3USICNT3
- 2USICNT2
- 1USICNT1
- 0USICNT0
5 fields
| Field | Bits | What it does |
|---|
| USISIF | 7 | Start Condition Interrupt Flag |
| USIOIF | 6 | Counter Overflow Interrupt Flag |
| USIPF | 5 | Stop Condition Flag |
| USIDC | 4 | Data Output Collision |
| USICNT | 3:0 | USI Counter Value Bits |
USIDRUSI Data Register
- Address
0x2F I/O 0x0F
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
PORTD I/O Port
PINDInput Pins, Port D
- Address
0x30 I/O 0x10
- Reset
0x00
- Access
- read/write
- 7–
- 6PIND6
- 5PIND5
- 4PIND4
- 3PIND3
- 2PIND2
- 1PIND1
- 0PIND0
DDRDData Direction Register, Port D
- Address
0x31 I/O 0x11
- Reset
0x00
- Access
- read/write
- 7–
- 6DDD6
- 5DDD5
- 4DDD4
- 3DDD3
- 2DDD2
- 1DDD1
- 0DDD0
PORTDData Register, Port D
- Address
0x32 I/O 0x12
- Reset
0x00
- Access
- read/write
- 7–
- 6PORTD6
- 5PORTD5
- 4PORTD4
- 3PORTD3
- 2PORTD2
- 1PORTD1
- 0PORTD0
CPU CPU Registers
GPIOR0General Purpose I/O Register 0
- Address
0x33 I/O 0x13
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
GPIOR1General Purpose I/O Register 1
- Address
0x34 I/O 0x14
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
GPIOR2General Purpose I/O Register 2
- Address
0x35 I/O 0x15
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
PCMSKPin-Change Mask register
- Address
0x40 I/O 0x20
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
GTCCRGeneral Timer Counter Control Register
- Address
0x43 I/O 0x23
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0PSR10
1 field
| Field | Bits | What it does |
|---|
| PSR10 | 0 | |
CLKPRClock Prescale Register
- Address
0x46 I/O 0x26
- Reset
0x00
- Access
- read/write
- 7CLKPCE
- 6–
- 5–
- 4–
- 3CLKPS3
- 2CLKPS2
- 1CLKPS1
- 0CLKPS0
2 fields
| Field | Bits | What it does |
|---|
| CLKPCE | 7 | Clock Prescaler Change Enable |
| CLKPS | 3:0 | Clock Prescaler Select Bits0 11 22 43 84 165 326 647 1288 256
|
OSCCALOscillator Calibration Register
- Address
0x51 I/O 0x31
- Reset
0x00
- Access
- read/write
- 7OSCCAL7
- 6OSCCAL6
- 5OSCCAL5
- 4OSCCAL4
- 3OSCCAL3
- 2OSCCAL2
- 1OSCCAL1
- 0OSCCAL0
1 field
| Field | Bits | What it does |
|---|
| OSCCAL | 7:0 | Oscillator Calibration |
MCUSRMCU Status register
- Address
0x54 I/O 0x34
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3WDRF
- 2BORF
- 1EXTRF
- 0PORF
4 fields
| Field | Bits | What it does |
|---|
| WDRF | 3 | Watchdog Reset Flag |
| BORF | 2 | Brown-out Reset Flag |
| EXTRF | 1 | External Reset Flag |
| PORF | 0 | Power-On Reset Flag |
MCUCRMCU Control Register
- Address
0x55 I/O 0x35
- Reset
0x00
- Access
- read/write
- 7PUD
- 6SM2
- 5SE
- 4SM0
- 3ISC11
- 2ISC10
- 1ISC01
- 0ISC00
5 fields
| Field | Bits | What it does |
|---|
| PUD | 7 | Pull-up Disable |
| SM | 6,4 | Sleep Mode Select Bits0 Idle1 Power Down4 Standby5 Power Down
|
| SE | 5 | Sleep Enable |
| ISC1 | 3:2 | Interrupt Sense Control 1 bits0 Low Level of INTX1 Any Logical Change in INTX2 Falling Edge of INTX3 Rising Edge of INTX
|
| ISC0 | 1:0 | Interrupt Sense Control 0 bits0 Low Level of INTX1 Any Logical Change in INTX2 Falling Edge of INTX3 Rising Edge of INTX
|
SPMCSRStore Program Memory Control and Status register
- Address
0x57 I/O 0x37
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4CTPB
- 3RFLB
- 2PGWRT
- 1PGERS
- 0SPMEN
5 fields
| Field | Bits | What it does |
|---|
| CTPB | 4 | Clear Temporary Page Buffer |
| RFLB | 3 | Read Fuse and Lock Bits |
| PGWRT | 2 | Page Write |
| PGERS | 1 | Page Erase |
| SPMEN | 0 | Store Program Memory Enable |
SPLStack Pointer Low Byte
- Address
0x5D I/O 0x3D
- Reset
0xDF
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
SREGStatus Register
- Address
0x5F I/O 0x3F
- Reset
0x00
- Access
- read/write
- 7I
- 6T
- 5H
- 4S
- 3V
- 2N
- 1Z
- 0C
8 fields
| Field | Bits | What it does |
|---|
| I | 7 | Global Interrupt Enable |
| T | 6 | Bit Copy Storage |
| H | 5 | Half Carry Flag |
| S | 4 | Sign Bit |
| V | 3 | Two's Complement Overflow Flag |
| N | 2 | Negative Flag |
| Z | 1 | Zero Flag |
| C | 0 | Carry Flag |
PORTB I/O Port
PINBPort B Input Pins
- Address
0x36 I/O 0x16
- Reset
0x00
- Access
- read/write
- 7PINB7
- 6PINB6
- 5PINB5
- 4PINB4
- 3PINB3
- 2PINB2
- 1PINB1
- 0PINB0
DDRBPort B Data Direction Register
- Address
0x37 I/O 0x17
- Reset
0x00
- Access
- read/write
- 7DDB7
- 6DDB6
- 5DDB5
- 4DDB4
- 3DDB3
- 2DDB2
- 1DDB1
- 0DDB0
PORTBPort B Data Register
- Address
0x38 I/O 0x18
- Reset
0x00
- Access
- read/write
- 7PORTB7
- 6PORTB6
- 5PORTB5
- 4PORTB4
- 3PORTB3
- 2PORTB2
- 1PORTB1
- 0PORTB0
PORTA I/O Port
PINAPort A Input Pins
- Address
0x39 I/O 0x19
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2PINA2
- 1PINA1
- 0PINA0
DDRAPort A Data Direction Register
- Address
0x3A I/O 0x1A
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2DDA2
- 1DDA1
- 0DDA0
PORTAPort A Data Register
- Address
0x3B I/O 0x1B
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2PORTA2
- 1PORTA1
- 0PORTA0
EEPROM EEPROM
EECREEPROM Control Register
- Address
0x3C I/O 0x1C
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5EEPM1
- 4EEPM0
- 3EERIE
- 2EEMPE
- 1EEPE
- 0EERE
5 fields
| Field | Bits | What it does |
|---|
| EEPM | 5:4 | 0 Erase and Write in one operation1 Erase Only2 Write Only
|
| EERIE | 3 | EEProm Ready Interrupt Enable |
| EEMPE | 2 | EEPROM Master Write Enable |
| EEPE | 1 | EEPROM Write Enable |
| EERE | 0 | EEPROM Read Enable |
EEDREEPROM Data Register
- Address
0x3D I/O 0x1D
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
EEAREEPROM Read/Write Access
- Address
0x3E I/O 0x1E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
WDT Watchdog Timer
WDTCRWatchdog Timer Control Register
- Address
0x41 I/O 0x21
- Reset
0x00
- Access
- read/write
- 7WDIF
- 6WDIE
- 5WDP5
- 4WDCE
- 3WDE
- 2WDP2
- 1WDP1
- 0WDP0
5 fields
| Field | Bits | What it does |
|---|
| WDIF | 7 | Watchdog Timeout Interrupt Flag |
| WDIE | 6 | Watchdog Timeout Interrupt Enable |
| WDP | 5,2,1,0 | Watchdog Timer Prescaler Bits0 Oscillator Cycles 2K1 Oscillator Cycles 4K2 Oscillator Cycles 8K3 Oscillator Cycles 16K4 Oscillator Cycles 32K5 Oscillator Cycles 64K6 Oscillator Cycles 128K7 Oscillator Cycles 256K8 Oscillator Cycles 512K9 Oscillator Cycles 1024K
|
| WDCE | 4 | Watchdog Change Enable |
| WDE | 3 | Watch Dog Enable |
TC1 Timer/Counter, 16-bit
TCCR1CTimer/Counter1 Control Register C
- Address
0x42 I/O 0x22
- Reset
0x00
- Access
- read/write
- 7FOC1A
- 6FOC1B
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|
| FOC1A | 7 | Force Output Compare for Channel A |
| FOC1B | 6 | Force Output Compare for Channel B |
ICR1Timer/Counter1 Input Capture Register Bytes
- Address
0x44 I/O 0x24
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
OCR1BTimer/Counter1 Output Compare Register Bytes
- Address
0x48 I/O 0x28
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
OCR1ATimer/Counter1 Output Compare Register Bytes
- Address
0x4A I/O 0x2A
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
TCNT1Timer/Counter1 Bytes
- Address
0x4C I/O 0x2C
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
TCCR1BTimer/Counter1 Control Register B
- Address
0x4E I/O 0x2E
- Reset
0x00
- Access
- read/write
- 7ICNC1
- 6ICES1
- 5–
- 4WGM11
- 3WGM10
- 2CS12
- 1CS11
- 0CS10
4 fields
| Field | Bits | What it does |
|---|
| ICNC1 | 7 | Input Capture 1 Noise Canceler |
| ICES1 | 6 | Input Capture 1 Edge Select |
| WGM1 | 4:3 | Waveform Generation Mode Bits |
| CS1 | 2:0 | Clock Select1 bits0 No Clock Source (Stopped)1 Running, No Prescaling2 Running, CLK/83 Running, CLK/644 Running, CLK/2565 Running, CLK/10246 Running, ExtClk Tn Falling Edge7 Running, ExtClk Tn Rising Edge
|
TCCR1ATimer/Counter1 Control Register A
- Address
0x4F I/O 0x2F
- Reset
0x00
- Access
- read/write
- 7COM1A1
- 6COM1A0
- 5COM1B1
- 4COM1B0
- 3–
- 2–
- 1WGM11
- 0WGM10
3 fields
| Field | Bits | What it does |
|---|
| COM1A | 7:6 | Compare Output Mode 1A, bits |
| COM1B | 5:4 | Compare Output Mode 1B, bits |
| WGM1 | 1:0 | Pulse Width Modulator Select Bits |
TIFRTimer/Counter Interrupt Flag register
- Address
0x58 I/O 0x38
- Reset
0x00
- Access
- read/write
- 7TOV1
- 6OCF1A
- 5OCF1B
- 4–
- 3ICF1
- 2–
- 1–
- 0–
4 fields
| Field | Bits | What it does |
|---|
| TOV1 | 7 | Timer/Counter1 Overflow Flag |
| OCF1A | 6 | Output Compare Flag 1A |
| OCF1B | 5 | Output Compare Flag 1B |
| ICF1 | 3 | Input Capture Flag 1 |
TIMSKTimer/Counter Interrupt Mask Register
- Address
0x59 I/O 0x39
- Reset
0x00
- Access
- read/write
- 7TOIE1
- 6OCIE1A
- 5OCIE1B
- 4–
- 3ICIE1
- 2–
- 1–
- 0–
4 fields
| Field | Bits | What it does |
|---|
| TOIE1 | 7 | Timer/Counter1 Overflow Interrupt Enable |
| OCIE1A | 6 | Timer/Counter1 Output CompareA Match Interrupt Enable |
| OCIE1B | 5 | Timer/Counter1 Output CompareB Match Interrupt Enable |
| ICIE1 | 3 | Timer/Counter1 Input Capture Interrupt Enable |
TC0 Timer/Counter, 8-bit
TCCR0ATimer/Counter Control Register A
- Address
0x50 I/O 0x30
- Reset
0x00
- Access
- read/write
- 7COM0A1
- 6COM0A0
- 5COM0B1
- 4COM0B0
- 3–
- 2–
- 1WGM01
- 0WGM00
3 fields
| Field | Bits | What it does |
|---|
| COM0A | 7:6 | Compare Match Output A Mode |
| COM0B | 5:4 | Compare Match Output B Mode |
| WGM0 | 1:0 | Waveform Generation Mode |
TCNT0Timer/Counter0
- Address
0x52 I/O 0x32
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TCCR0BTimer/Counter Control Register B
- Address
0x53 I/O 0x33
- Reset
0x00
- Access
- read/write
- 7FOC0A
- 6FOC0B
- 5–
- 4–
- 3WGM02
- 2CS02
- 1CS01
- 0CS00
4 fields
| Field | Bits | What it does |
|---|
| FOC0A | 7 | Force Output Compare B |
| FOC0B | 6 | Force Output Compare B |
| WGM02 | 3 | |
| CS0 | 2:0 | Clock Select0 No Clock Source (Stopped)1 Running, No Prescaling2 Running, CLK/83 Running, CLK/644 Running, CLK/2565 Running, CLK/10246 Running, ExtClk Tn Falling Edge7 Running, ExtClk Tn Rising Edge
|
OCR0ATimer/Counter0 Output Compare Register
- Address
0x56 I/O 0x36
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TIFRTimer/Counter Interrupt Flag register
- Address
0x58 I/O 0x38
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2OCF0B
- 1TOV0
- 0OCF0A
3 fields
| Field | Bits | What it does |
|---|
| OCF0B | 2 | Timer/Counter0 Output Compare Flag 0B |
| TOV0 | 1 | Timer/Counter0 Overflow Flag |
| OCF0A | 0 | Timer/Counter0 Output Compare Flag 0A |
TIMSKTimer/Counter Interrupt Mask Register
- Address
0x59 I/O 0x39
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2OCIE0B
- 1TOIE0
- 0OCIE0A
3 fields
| Field | Bits | What it does |
|---|
| OCIE0B | 2 | Timer/Counter0 Output Compare Match B Interrupt Enable |
| TOIE0 | 1 | Timer/Counter0 Overflow Interrupt Enable |
| OCIE0A | 0 | Timer/Counter0 Output Compare Match A Interrupt Enable |
OCR0BTimer/Counter0 Output Compare Register
- Address
0x5C I/O 0x3C
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
EXINT External Interrupts
EIFRExtended Interrupt Flag Register
- Address
0x5A I/O 0x3A
- Reset
0x00
- Access
- read/write
- 7INTF1
- 6INTF0
- 5PCIF
- 4–
- 3–
- 2–
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|
| INTF | 7:6 | External Interrupt Flags |
| PCIF | 5 | |
GIMSKGeneral Interrupt Mask Register
- Address
0x5B I/O 0x3B
- Reset
0x00
- Access
- read/write
- 7INT1
- 6INT0
- 5PCIE
- 4–
- 3–
- 2–
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|
| INT | 7:6 | External Interrupt Request 1 Enable |
| PCIE | 5 | |