ATtiny828 fuses & lock bits
The fuse bytes set the clock, start-up, brown-out and boot options; the lock bits protect flash and EEPROM. A fuse bit is programmed at 0 . Change a setting and the byte below updates; the starting values are the factory defaults.
CKDIV8 Divide clock by 8 internally 1 · unprogrammed 0 · programmed CKOUT Clock output on PORTB0 1 · unprogrammed 0 · programmed SUT_CKSEL Select Clock Source Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms HIGH fuse 0xDF default 0xDF RSTDISBL Reset Disabled (Enable PC6 as i/o pin)] 1 · unprogrammed 0 · programmed DWEN Debug Wire enable 1 · unprogrammed 0 · programmed SPIEN Serial program downloading (SPI) enabled 1 · unprogrammed 0 · programmed WDTON Watch-dog Timer always on 1 · unprogrammed 0 · programmed EESAVE Preserve EEPROM through the Chip Erase cycle 1 · unprogrammed 0 · programmed BODLEVEL Brown-out Detector trigger level Brown-out detection at VCC=4.3 V Brown-out detection at VCC=2.7 V Brown-out detection at VCC=1.8 V Brown-out detection disabled EXTENDED fuse 0xFF default 0xFF BODPD BOD mode of operation when the device is in sleep mode Sampled Enabled Disabled BODACT BOD mode of operation when the device is active or idle Sampled Enabled Disabled BOOTSZ Select boot size Boot Flash size=1024 words Boot address=$0C00 Boot Flash size=512 words Boot address=$0E00 Boot Flash size=256 words Boot address=$0F00 Boot Flash size=128 words Boot address=$0F80 BOOTRST Boot Reset vector Enabled 1 · unprogrammed 0 · programmed Lock bits 0xFF default 0xFF BLB1 Boot Loader Protection Mode LPM and SPM prohibited in Boot Section LPM prohibited in Boot Section SPM prohibited in Boot Section No lock on SPM and LPM in Boot Section BLB0 Boot Loader Protection Mode LPM and SPM prohibited in Application Section LPM prohibited in Application Section SPM prohibited in Application Section No lock on SPM and LPM in Application Section LB Memory Lock Further programming and verification disabled Further programming disabled No memory lock features enabled