dsPIC30F5011 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FOSC · 0xF80000 0xFDF0 default 0xFDF0 FCKSMEN Clock Switching and Monitor Sw Enabled, Mon Enabled Sw Enabled, Mon Disabled Sw Disabled, Mon Disabled 3 (not named) FOS Oscillator Source Low-Power 32KHz Osc <TMR1 Osc> Internal Fast RC Internal Low-Power RC Primary Oscillator FPR Primary Oscillator Mode XTL FRC w/ PLL 4x HS FRC w/ PLL 16x XT XT w/PLL 4x XT w/PLL 8x XT w/PLL 16x ERCIO ERC FRC w/ PLL 8x EC ECIO ECIO w/ PLL 4x ECIO w/ PLL 8x ECIO w/ PLL 16x FWDT · 0xF80002 0xFFFF default 0xFFFF WDT Watchdog Timer Disabled Enabled FWPSA WDT Prescaler A 1:1 1:8 1:64 1:512 FWPSB WDT Prescaler B 1:1 1:2 1:3 1:4 1:5 1:6 1:7 1:8 1:9 1:10 1:11 1:12 1:13 1:14 1:15 1:16 FBORPOR · 0xF80004 0xFFFF default 0xFFFF MCLRE Master Clear Enable Disabled Enabled RES0 Reserved Reserved BOREN PBOR Enable Disabled Enabled BODENV Brown Out Voltage 4.5V 4.2V 2.7V 2.0V FPWRT POR Timer Value Timer Disabled 4ms 16ms 64ms FBS · 0xF80006 0xFFFF default 0xFFFF RBS Boot Segment Data RAM Protection Large-sized Boot RAM Medium-sized Boot RAM Small-sized Boot RAM No Boot RAM EBS Boot Segment Data EEPROM Protection Boot EEPROM Enabled No Boot EEPROM BSS Boot Segment Program Flash Memory Code Protection High Security, Large-sized Boot Flash High Security, Medium-sized Boot Flash High Security, Small-sized Boot Flash Standard Security, Large-sized Boot Flash Standard Security, Medium-sized Boot Flash Standard Security, Small-sized Boot Flash No Boot Segment BWRP Boot Segment Program Memory Write Protect Boot Segment Program Memory is write protected Boot Segment Program Memory may be written FSS · 0xF80008 0xFFFF default 0xFFFF RSS Secure Segment Data RAM Protection Large-sized Secure RAM Medium-sized Secure RAM Small-sized Secure RAM No Secure RAM ESS Secure Segment Data EEPROM Protection Large-sized Secure Data EEPROM Medium-sized Secure Data EEPROM Small-sized Secure Data EEPROM No Segment Data EEPROM SSS Secure Segment Program Flash Memory Code Protection High Security, Large-sized Secure Flash High Security, Medium-sized Secure Flash High Security, Small-sized Secure Flash Standard Security, Large-sized Secure Flash Standard Security, Medium-sized Secure Flash Standard Security, Small-sized Secure Flash No Secure Segment SWRP Secure Segment Program Write Protect Enabled Disabled FGS · 0xF8000A 0xFFFF default 0xFFFF GCP General Segment Code Protection High Security Code Protection Enabled Enabled Disabled GWRP General Code Segment Write Protect Enabled Disabled FICD · 0xF8000C 0xFFFF default 0xFFFF BACKBUG Background Debug Enabled Disabled COE Set Clip On Emulation Mode Reset Into Clip On Emulation Mode Reset Into Operational Mode ICS Comm Channel Select Use EMUC3 and EMUD3 Use EMUC2 and EMUD2 Use EMUC1 and EMUD1 Use PGC/EMUC and PGD/EMUD