dsPIC33CH64MP203 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x00AF00), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0xAF00 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table bit Enabled AIVT Disabled AIVT CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0xAF10 0xFFFFFF default 0xFFFFFF BSLIM Boot Segment Flash Page Address Limit bits FSIGN · 0xAF14 0xFF7FFF default 0xFF7FFF FSIGN Sign Bit Configuration FOSCSEL · 0xAF18 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Low-Power RC Oscillator (LPRC) Back up Fast RC (BFRC) Oscillator Internal Fast RC (FRC) Oscillator with postscaler FOSC · 0xAF1C 0xFFFFFF default 0xFFFFFF XTBST XT Boost Default kick-start Boost the kick-start XTCFG XT Config 4-8 MHz crystals 8-16 MHz crystals 16-24 MHz crystals 24-32 MHz crystals PLLKEN PLLKEN reserved as PLLKEN_ON reserved as PLLKEN_ON FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) OSCIOFNC OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select bits EC (External Clock) Mode XT Crystal Oscillator Mode HS Crystal Oscillator Mode Primary Oscillator disabled FWDT · 0xAF20 0xFFFFFF default 0xFFFFFF FWDTEN Watchdog Timer Enable bit WDT controlled via SW, use WDTCON.ON bit WDT enabled in hardware SWDTPS Sleep Mode Watchdog Timer Post Scaler select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 31 (not named) WDTWIN Watchdog Timer Window Select bits WDT Windo is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period WINDIS Watchdog Timer Window Enable bit Watchdog Timer operates in Window mode Watchdog Timer operates in Non-Window mode RCLKSEL Watchdog Timer Clock Select bits Use peripheral clk when system clock is not INTOSC/LPRC and device is not in Sleep;otherwise, use INTOSC/LPRC Use FRC when WINDIS = 0, system clock is not INTOSC/LPRC and device is not in Sleep;otherwise, use INTOSC/LPRC Always use LPRC RWDTPS Run Mode Watchdog Timer Post Scaler select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 31 (not named) FICD · 0xAF28 0xFFFFDF default 0xFFFFDF JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGC3 and PGD3 Communicate on PGC2 and PGD2 Communicate on PGC1 and PGD1 FDMTIVTL · 0xAF2C 0xFFFFFF default 0xFFFFFF DMTIVTL Dead Man Timer Interval low word FDMTIVTH · 0xAF30 0xFFFFFF default 0xFFFFFF DMTIVTH Dead Man Timer Interval high word FDMTCNTL · 0xAF34 0xFFFFFF default 0xFFFFFF DMTCNTL Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) FDMTCNTH · 0xAF38 0xFFFFFF default 0xFFFFFF DMTCNTH Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) FDMT · 0xAF3C 0xFFFFFF default 0xFFFFFF DMTDIS Dead Man Timer Disable bit Dead Man Timer is Enabled and cannot be disabled by software Dead Man Timer is Disabled and can be enabled by software FDEVOPT · 0xAF40 0xFFFFFF default 0xFFFFFF SPI2PIN SPI2 Pin Select bit SPI2 uses dedicated I/O pins SPI2 uses I/O remap (PPS) pins SMBEN SM Bus Enable Standard I2C input threshold operation SMBus input threshold is enabled ALTI2C2 Alternate I2C2 Pin bit I2C2 mapped to ASDA2/ASCL2 pins I2C2 mapped to SDA2/SCL2 pins ALTI2C1 Alternate I2C1 Pin bit I2C1 mapped to ASDA1/ASCL1 pins I2C1 mapped to SDA1/SCL1 pins FALTREG · 0xAF44 0xFFFFFF default 0xFFFFFF CTXT4 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT3 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT2 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT1 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned FMBXM · 0xAF48 0xFFFFFF default 0xFFFFFF MBXM15 Mailbox 15 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM14 Mailbox 14 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM13 Mailbox 13 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM12 Mailbox 12 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM11 Mailbox 11 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM10 Mailbox 10 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM9 Mailbox 9 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM8 Mailbox 8 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM7 Mailbox 7 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM6 Mailbox 6 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM5 Mailbox 5 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM4 Mailbox 4 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM3 Mailbox 3 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM2 Mailbox 2 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM1 Mailbox 1 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) MBXM0 Mailbox 0 data direction Mailbox register configured for Main data write (Main to Secondary data transfer) Mailbox register configured for Main data read (Secondary to Main data transfer) FMBXHS1 · 0xAF4C 0xFFFFFF default 0xFFFFFF MBXHSD Mailbox handshake protocol block D register assignment MSIxMBXD0 assigned to mailbox handshake protocol block D MSIxMBXD1 assigned to mailbox handshake protocol block D MSIxMBXD2 assigned to mailbox handshake protocol block D MSIxMBXD3 assigned to mailbox handshake protocol block D MSIxMBXD4 assigned to mailbox handshake protocol block D MSIxMBXD5 assigned to mailbox handshake protocol block D MSIxMBXD6 assigned to mailbox handshake protocol block D MSIxMBXD7 assigned to mailbox handshake protocol block D MSIxMBXD8 assigned to mailbox handshake protocol block D MSIxMBXD9 assigned to mailbox handshake protocol block D MSIxMBXD10 assigned to mailbox handshake protocol block D MSIxMBXD11 assigned to mailbox handshake protocol block D MSIxMBXD12 assigned to mailbox handshake protocol block D MSIxMBXD13 assigned to mailbox handshake protocol block D MSIxMBXD14 assigned to mailbox handshake protocol block D MSIxMBXD15 assigned to mailbox handshake protocol block D MBXHSC Mailbox handshake protocol block C register assignment MSIxMBXD0 assigned to mailbox handshake protocol block C MSIxMBXD1 assigned to mailbox handshake protocol block C MSIxMBXD2 assigned to mailbox handshake protocol block C MSIxMBXD3 assigned to mailbox handshake protocol block C MSIxMBXD4 assigned to mailbox handshake protocol block C MSIxMBXD5 assigned to mailbox handshake protocol block C MSIxMBXD6 assigned to mailbox handshake protocol block C MSIxMBXD7 assigned to mailbox handshake protocol block C MSIxMBXD8 assigned to mailbox handshake protocol block C MSIxMBXD9 assigned to mailbox handshake protocol block C MSIxMBXD10 assigned to mailbox handshake protocol block C MSIxMBXD11 assigned to mailbox handshake protocol block C MSIxMBXD12 assigned to mailbox handshake protocol block C MSIxMBXD13 assigned to mailbox handshake protocol block C MSIxMBXD14 assigned to mailbox handshake protocol block C MSIxMBXD15 assigned to mailbox handshake protocol block C MBXHSB Mailbox handshake protocol block B register assignment MSIxMBXD0 assigned to mailbox handshake protocol block B MSIxMBXD1 assigned to mailbox handshake protocol block B MSIxMBXD2 assigned to mailbox handshake protocol block B MSIxMBXD3 assigned to mailbox handshake protocol block B MSIxMBXD4 assigned to mailbox handshake protocol block B MSIxMBXD5 assigned to mailbox handshake protocol block B MSIxMBXD6 assigned to mailbox handshake protocol block B MSIxMBXD7 assigned to mailbox handshake protocol block B MSIxMBXD8 assigned to mailbox handshake protocol block B MSIxMBXD9 assigned to mailbox handshake protocol block B MSIxMBXD10 assigned to mailbox handshake protocol block B MSIxMBXD11 assigned to mailbox handshake protocol block B MSIxMBXD12 assigned to mailbox handshake protocol block B MSIxMBXD13 assigned to mailbox handshake protocol block B MSIxMBXD14 assigned to mailbox handshake protocol block B MSIxMBXD15 assigned to mailbox handshake protocol block B MBXHSA Mailbox handshake protocol block A register assignment MSIxMBXD0 assigned to mailbox handshake protocol block A MSIxMBXD1 assigned to mailbox handshake protocol block A MSIxMBXD2 assigned to mailbox handshake protocol block A MSIxMBXD3 assigned to mailbox handshake protocol block A MSIxMBXD4 assigned to mailbox handshake protocol block A MSIxMBXD5 assigned to mailbox handshake protocol block A MSIxMBXD6 assigned to mailbox handshake protocol block A MSIxMBXD7 assigned to mailbox handshake protocol block A MSIxMBXD8 assigned to mailbox handshake protocol block A MSIxMBXD9 assigned to mailbox handshake protocol block A MSIxMBXD10 assigned to mailbox handshake protocol block A MSIxMBXD11 assigned to mailbox handshake protocol block A MSIxMBXD12 assigned to mailbox handshake protocol block A MSIxMBXD13 assigned to mailbox handshake protocol block A MSIxMBXD14 assigned to mailbox handshake protocol block A MSIxMBXD15 assigned to mailbox handshake protocol block A FMBXHS2 · 0xAF50 0xFFFFFF default 0xFFFFFF MBXHSH Mailbox handshake protocol block H register assignment MSIxMBXD0 assigned to mailbox handshake protocol block H MSIxMBXD1 assigned to mailbox handshake protocol block H MSIxMBXD2 assigned to mailbox handshake protocol block H MSIxMBXD3 assigned to mailbox handshake protocol block H MSIxMBXD4 assigned to mailbox handshake protocol block H MSIxMBXD5 assigned to mailbox handshake protocol block H MSIxMBXD6 assigned to mailbox handshake protocol block H MSIxMBXD7 assigned to mailbox handshake protocol block H MSIxMBXD8 assigned to mailbox handshake protocol block H MSIxMBXD9 assigned to mailbox handshake protocol block H MSIxMBXD10 assigned to mailbox handshake protocol block H MSIxMBXD11 assigned to mailbox handshake protocol block H MSIxMBXD12 assigned to mailbox handshake protocol block H MSIxMBXD13 assigned to mailbox handshake protocol block H MSIxMBXD14 assigned to mailbox handshake protocol block H MSIxMBXD15 assigned to mailbox handshake protocol block H MBXHSG Mailbox handshake protocol block G register assignment MSIxMBXD0 assigned to mailbox handshake protocol block G MSIxMBXD1 assigned to mailbox handshake protocol block G MSIxMBXD2 assigned to mailbox handshake protocol block G MSIxMBXD3 assigned to mailbox handshake protocol block G MSIxMBXD4 assigned to mailbox handshake protocol block G MSIxMBXD5 assigned to mailbox handshake protocol block G MSIxMBXD6 assigned to mailbox handshake protocol block G MSIxMBXD7 assigned to mailbox handshake protocol block G MSIxMBXD8 assigned to mailbox handshake protocol block G MSIxMBXD9 assigned to mailbox handshake protocol block G MSIxMBXD10 assigned to mailbox handshake protocol block G MSIxMBXD11 assigned to mailbox handshake protocol block G MSIxMBXD12 assigned to mailbox handshake protocol block G MSIxMBXD13 assigned to mailbox handshake protocol block G MSIxMBXD14 assigned to mailbox handshake protocol block G MSIxMBXD15 assigned to mailbox handshake protocol block G MBXHSF Mailbox handshake protocol block F register assignment MSIxMBXD0 assigned to mailbox handshake protocol block F MSIxMBXD1 assigned to mailbox handshake protocol block F MSIxMBXD2 assigned to mailbox handshake protocol block F MSIxMBXD3 assigned to mailbox handshake protocol block F MSIxMBXD4 assigned to mailbox handshake protocol block F MSIxMBXD5 assigned to mailbox handshake protocol block F MSIxMBXD6 assigned to mailbox handshake protocol block F MSIxMBXD7 assigned to mailbox handshake protocol block F MSIxMBXD8 assigned to mailbox handshake protocol block F MSIxMBXD9 assigned to mailbox handshake protocol block F MSIxMBXD10 assigned to mailbox handshake protocol block F MSIxMBXD11 assigned to mailbox handshake protocol block F MSIxMBXD12 assigned to mailbox handshake protocol block F MSIxMBXD13 assigned to mailbox handshake protocol block F MSIxMBXD14 assigned to mailbox handshake protocol block F MSIxMBXD15 assigned to mailbox handshake protocol block F MBXHSE Mailbox handshake protocol block E register assignment MSIxMBXD0 assigned to mailbox handshake protocol block E MSIxMBXD1 assigned to mailbox handshake protocol block E MSIxMBXD2 assigned to mailbox handshake protocol block E MSIxMBXD3 assigned to mailbox handshake protocol block E MSIxMBXD4 assigned to mailbox handshake protocol block E MSIxMBXD5 assigned to mailbox handshake protocol block E MSIxMBXD6 assigned to mailbox handshake protocol block E MSIxMBXD7 assigned to mailbox handshake protocol block E MSIxMBXD8 assigned to mailbox handshake protocol block E MSIxMBXD9 assigned to mailbox handshake protocol block E MSIxMBXD10 assigned to mailbox handshake protocol block E MSIxMBXD11 assigned to mailbox handshake protocol block E MSIxMBXD12 assigned to mailbox handshake protocol block E MSIxMBXD13 assigned to mailbox handshake protocol block E MSIxMBXD14 assigned to mailbox handshake protocol block E MSIxMBXD15 assigned to mailbox handshake protocol block E FMBXHSEN · 0xAF54 0xFFFFFF default 0xFFFFFF HSHEN Mailbox H data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSGEN Mailbox G data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSFEN Mailbox F data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSEEN Mailbox E data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSDEN Mailbox D data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSCEN Mailbox C data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSBEN Mailbox B data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. HSAEN Mailbox A data flow control protocol block enable Mailbox data flow control handshake protocol block enabled Mailbox data flow control handshake protocol block disabled. FCFGPRA0 · 0xAF58 0xFFFFFF default 0xFFFFFF CPRA4 Pin RA4 Ownership Bits Secondary core owns pin. Main core owns pin. CPRA3 Pin RA3 Ownership Bits Secondary core owns pin. Main core owns pin. CPRA2 Pin RA2 Ownership Bits Secondary core owns pin. Main core owns pin. CPRA1 Pin RA1 Ownership Bits Secondary core owns pin. Main core owns pin. CPRA0 Pin RA0 Ownership Bits Secondary core owns pin. Main core owns pin. FCFGPRB0 · 0xAF60 0xFFFFFF default 0xFFFFFF CPRB15 Pin RB15 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB14 Pin RB14 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB13 Pin RB13 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB12 Pin RB12 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB11 Pin RB11 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB10 Pin RB10 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB9 Pin RB9 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB8 Pin RB8 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB7 Pin RB7 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB6 Pin RB6 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB5 Pin RB5 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB4 Pin RB4 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB3 Pin RB3 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB2 Pin RB2 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB1 Pin RB1 Ownership Bits Secondary core owns pin. Main core owns pin. CPRB0 Pin RB0 Ownership Bits Secondary core owns pin. Main core owns pin. FCFGPRC0 · 0xAF68 0xFFFFFF default 0xFFFFFF CPRC15 Pin RC15 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC14 Pin RC14 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC13 Pin RC13 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC12 Pin RC12 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC11 Pin RC11 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC10 Pin RC10 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC9 Pin RC9 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC8 Pin RC8 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC7 Pin RC7 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC6 Pin RC6 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC5 Pin RC5 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC4 Pin RC4 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC3 Pin RC3 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC2 Pin RC2 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC1 Pin RC1 Ownership Bits Secondary core owns pin. Main core owns pin. CPRC0 Pin RC0 Ownership Bits Secondary core owns pin. Main core owns pin. FCFGPRD0 · 0xAF70 0xFFFFFF default 0xFFFFFF CPRD15 Pin RD15 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD14 Pin RD14 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD13 Pin RD13 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD12 Pin RD12 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD11 Pin RD11 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD10 Pin RD10 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD9 Pin RD9 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD8 Pin RD8 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD7 Pin RD7 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD6 Pin RD6 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD5 Pin RD5 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD4 Pin RD4 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD3 Pin RD3 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD2 Pin RD2 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD1 Pin RD1 Ownership Bits Secondary core owns pin. Main core owns pin. CPRD0 Pin RD0 Ownership Bits Secondary core owns pin. Main core owns pin. FCFGPRE0 · 0xAF78 0xFFFFFF default 0xFFFFFF CPRE15 Pin RE15 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE14 Pin RE14 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE13 Pin RE13 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE12 Pin RE12 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE11 Pin RE11 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE10 Pin RE10 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE9 Pin RE9 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE8 Pin RE8 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE7 Pin RE7 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE6 Pin RE6 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE5 Pin RE5 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE4 Pin RE4 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE3 Pin RE3 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE2 Pin RE2 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE1 Pin RE1 Ownership Bits Secondary core owns pin. Main core owns pin. CPRE0 Pin RE0 Ownership Bits Secondary core owns pin. Main core owns pin. FS1OSCSEL · 0xAF80 0xFFFFFF default 0xFFFFFF S1IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source S1FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Low-Power RC Oscillator (LPRC) Back up Fast RC (BFRC) Oscillator Internal Fast RC (FRC) Oscillator with postscaler FS1OSC · 0xAF84 0xFFFFFF default 0xFFFFFF S1PLLKEN S1PLLKEN reserved as S1PLLKEN_ON reserved as S1PLLKEN_ON S1FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) S1OSCIOFNC Secondary OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output FS1WDT · 0xAF88 0xFFFFFF default 0xFFFFFF S1FWDTEN Watchdog Timer Enable bit WDT controlled via WDTCON.ON bit WDT enabled in hardware S1SWDTPS Sleep Mode Watchdog Timer Post Scaler select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 31 (not named) S1WDTWIN Watchdog Timer Window Select bits WDT Windo is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period S1WINDIS Watchdog Timer Window Enable bit Watchdog Timer operates in Window mode Watchdog Timer operates in Non-Window mode S1RCLKSEL Watchdog Timer Clock Select bits Use peripheral clk when system clock is not INTOSC/LPRC and device is not in Sleep;otherwise, use INTOSC/LPRC Use FRC when WINDIS = 0, system clock is not INTOSC/LPRC and device is not in Sleep; otherwise, use INTOSC/LPRC Always use LPRC S1RWDTPS Run Mode Watchdog Timer Post Scaler select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 31 (not named) FS1ICD · 0xAF90 0xFFFFFF default 0xFFFFFF S1NOBTSWP BOOTSWP Instruction Enable/Disable bit BOOTSWP instruction is enabled BOOTSWP instruction is disabled S1ISOLAT Isolate the Secondary core subsystem from the Main subsystem during Debug The Secondary can only operate if the SLVEN bit in the MSI is set. The Secondary can operate (in debug mode) even if the SLVEN bit in the MSI is zero. S1ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGC3 and PGD3 Communicate on PGC2 and PGD2 Communicate on PGC1 and PGD1 FS1DEVOPT · 0xAF94 0xFFFFFF default 0xFFFFFF S1MSRE Main Secondary Reset Enable The Main software oriented RESET events (RESET Op-Code, Watchdog timeout, TRAP reset, illegalInstruction) will not cause the Secondary subsystem to reset. The Main software oriented RESET events (RESET Op-Code, Watchdog timeout, TRAP reset, illegalInstruction) will also cause the Secondary subsystem to reset. S1SSRE Secondary Secondary Reset Enable Secondary generated resets will not reset the Secondary Enable Bit in the MSI module Secondary generated resets will reset the Secondary Enable Bit in the MSI module S1SPI1PIN S1 SPI1 Pin Select bit Secondary SPI1 uses dedicated I/O pins Secondary SPI1 uses I/O remap (PPS) pins S1ALTI2C1 Alternate I2C1 Pin bit I2C1 mapped to ASDA1/ASCL1 pins I2C1 mapped to SDA1/SCL1 pins FS1ALTREG · 0xAF98 0xFFFFFF default 0xFFFFFF S1CTXT4 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned S1CTXT3 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned S1CTXT2 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned S1CTXT1 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned 
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