dsPIC33CK256MP506 peripherals

Each block of the dsPIC33CK256MP506: what it is, the registers that control it and the pins it uses.

CPU

CPU

CPU core (W registers, DSP, program space)

Registers

ADC

ADC

Analog-to-digital converter

Registers

Pins

CAN1

CAN

CAN bus 1

Registers

C1CONL0x5C0C1CONH0x5C2C1NBTCFGL0x5C4C1NBTCFGH0x5C6C1DBTCFGL0x5C8C1DBTCFGH0x5CAC1TDCL0x5CCC1TDCH0x5CEC1TBCL0x5D0C1TBCH0x5D2C1TSCONL0x5D4C1TSCONH0x5D6C1VECL0x5D8C1VECH0x5DAC1INTL0x5DCC1INTH0x5DEC1RXIFL0x5E0C1RXIFH0x5E2C1TXIFL0x5E4C1TXIFH0x5E6C1RXOVIFL0x5E8C1RXOVIFH0x5EAC1TXATIFL0x5ECC1TXATIFH0x5EEC1TXREQL0x5F0C1TXREQH0x5F2C1TRECL0x5F4C1TRECH0x5F6C1BDIAG0L0x5F8C1BDIAG0H0x5FAC1BDIAG1L0x5FCC1BDIAG1H0x5FEC1TEFCONL0x600C1TEFCONH0x602C1TEFSTA0x604C1TEFUAL0x608C1TEFUAH0x60AC1FIFOBAL0x60CC1FIFOBAH0x60EC1TXQCONL0x610C1TXQCONH0x612C1TXQSTA0x614C1TXQUAL0x618C1TXQUAH0x61AC1FIFOCON1L0x61CC1FIFOCON1H0x61EC1FIFOSTA10x620C1FIFOUA1L0x624C1FIFOUA1H0x626C1FIFOCON2L0x628C1FIFOCON2H0x62AC1FIFOSTA20x62CC1FIFOUA2L0x630C1FIFOUA2H0x632C1FIFOCON3L0x634C1FIFOCON3H0x636C1FIFOSTA30x638C1FIFOUA3L0x63CC1FIFOUA3H0x63EC1FIFOCON4L0x640C1FIFOCON4H0x642C1FIFOSTA40x644C1FIFOUA4L0x648C1FIFOUA4H0x64AC1FIFOCON5L0x64CC1FIFOCON5H0x64EC1FIFOSTA50x650C1FIFOUA5L0x654C1FIFOUA5H0x656C1FIFOCON6L0x658C1FIFOCON6H0x65AC1FIFOSTA60x65CC1FIFOUA6L0x660C1FIFOUA6H0x662C1FIFOCON7L0x664C1FIFOCON7H0x666C1FIFOSTA70x668C1FIFOUA7L0x66CC1FIFOUA7H0x66EC1FLTCON0L0x670C1FLTCON0H0x672C1FLTCON1L0x674C1FLTCON1H0x676C1FLTCON2L0x678C1FLTCON2H0x67AC1FLTCON3L0x67CC1FLTCON3H0x67EC1FLTOBJ0L0x680C1FLTOBJ0H0x682C1MASK0L0x684C1MASK0H0x686C1FLTOBJ1L0x688C1FLTOBJ1H0x68AC1MASK1L0x68CC1MASK1H0x68EC1FLTOBJ2L0x690C1FLTOBJ2H0x692C1MASK2L0x694C1MASK2H0x696C1FLTOBJ3L0x698C1FLTOBJ3H0x69AC1MASK3L0x69CC1MASK3H0x69EC1FLTOBJ4L0x6A0C1FLTOBJ4H0x6A2C1MASK4L0x6A4C1MASK4H0x6A6C1FLTOBJ5L0x6A8C1FLTOBJ5H0x6AAC1MASK5L0x6ACC1MASK5H0x6AEC1FLTOBJ6L0x6B0C1FLTOBJ6H0x6B2C1MASK6L0x6B4C1MASK6H0x6B6C1FLTOBJ7L0x6B8C1FLTOBJ7H0x6BAC1MASK7L0x6BCC1MASK7H0x6BEC1FLTOBJ8L0x6C0C1FLTOBJ8H0x6C2C1MASK8L0x6C4C1MASK8H0x6C6C1FLTOBJ9L0x6C8C1FLTOBJ9H0x6CAC1MASK9L0x6CCC1MASK9H0x6CEC1FLTOBJ10L0x6D0C1FLTOBJ10H0x6D2C1MASK10L0x6D4C1MASK10H0x6D6C1FLTOBJ11L0x6D8C1FLTOBJ11H0x6DAC1MASK11L0x6DCC1MASK11H0x6DEC1FLTOBJ12L0x6E0C1FLTOBJ12H0x6E2C1MASK12L0x6E4C1MASK12H0x6E6C1FLTOBJ13L0x6E8C1FLTOBJ13H0x6EAC1MASK13L0x6ECC1MASK13H0x6EEC1FLTOBJ14L0x6F0C1FLTOBJ14H0x6F2C1MASK14L0x6F4C1MASK14H0x6F6C1FLTOBJ15L0x6F8C1FLTOBJ15H0x6FAC1MASK15L0x6FCC1MASK15H0x6FE

INTERRUPT

INTERRUPT

Interrupts

Registers

Pins

POWER

POWER

Low-power and deep sleep control

Registers

PPS

PPS

Peripheral pin select

Registers

PWM

PWM

PWM generators

Registers

PCLKCON0x300FSCL0x302FSMINPER0x304MPHASE0x306MDC0x308MPER0x30ALFSR0x30CCMBTRIGL0x30ECMBTRIGH0x310LOGCONA0x312LOGCONB0x314LOGCONC0x316LOGCOND0x318LOGCONE0x31ALOGCONF0x31CPWMEVTA0x31EPWMEVTB0x320PWMEVTC0x322PWMEVTD0x324PWMEVTE0x326PWMEVTF0x328PG1CONL0x32APG1CONH0x32CPG1STAT0x32EPG1IOCONL0x330PG1IOCONH0x332PG1EVTL0x334PG1EVTH0x336PG1FPCIL0x338PG1FPCIH0x33APG1CLPCIL0x33CPG1CLPCIH0x33EPG1FFPCIL0x340PG1FFPCIH0x342PG1SPCIL0x344PG1SPCIH0x346PG1LEBL0x348PG1LEBH0x34APG1PHASE0x34CPG1DC0x34EPG1DCA0x350PG1PER0x352PG1TRIGA0x354PG1TRIGB0x356PG1TRIGC0x358PG1DTL0x35APG1DTH0x35CPG1CAP0x35EPG2CONL0x360PG2CONH0x362PG2STAT0x364PG2IOCONL0x366PG2IOCONH0x368PG2EVTL0x36APG2EVTH0x36CPG2FPCIL0x36EPG2FPCIH0x370PG2CLPCIL0x372PG2CLPCIH0x374PG2FFPCIL0x376PG2FFPCIH0x378PG2SPCIL0x37APG2SPCIH0x37CPG2LEBL0x37EPG2LEBH0x380PG2PHASE0x382PG2DC0x384PG2DCA0x386PG2PER0x388PG2TRIGA0x38APG2TRIGB0x38CPG2TRIGC0x38EPG2DTL0x390PG2DTH0x392PG2CAP0x394PG3CONL0x396PG3CONH0x398PG3STAT0x39APG3IOCONL0x39CPG3IOCONH0x39EPG3EVTL0x3A0PG3EVTH0x3A2PG3FPCIL0x3A4PG3FPCIH0x3A6PG3CLPCIL0x3A8PG3CLPCIH0x3AAPG3FFPCIL0x3ACPG3FFPCIH0x3AEPG3SPCIL0x3B0PG3SPCIH0x3B2PG3LEBL0x3B4PG3LEBH0x3B6PG3PHASE0x3B8PG3DC0x3BAPG3DCA0x3BCPG3PER0x3BEPG3TRIGA0x3C0PG3TRIGB0x3C2PG3TRIGC0x3C4PG3DTL0x3C6PG3DTH0x3C8PG3CAP0x3CAPG4CONL0x3CCPG4CONH0x3CEPG4STAT0x3D0PG4IOCONL0x3D2PG4IOCONH0x3D4PG4EVTL0x3D6PG4EVTH0x3D8PG4FPCIL0x3DAPG4FPCIH0x3DCPG4CLPCIL0x3DEPG4CLPCIH0x3E0PG4FFPCIL0x3E2PG4FFPCIH0x3E4PG4SPCIL0x3E6PG4SPCIH0x3E8PG4LEBL0x3EAPG4LEBH0x3ECPG4PHASE0x3EEPG4DC0x3F0PG4DCA0x3F2PG4PER0x3F4PG4TRIGA0x3F6PG4TRIGB0x3F8PG4TRIGC0x3FAPG4DTL0x3FCPG4DTH0x3FEPG4CAP0x400PG5CONL0x402PG5CONH0x404PG5STAT0x406PG5IOCONL0x408PG5IOCONH0x40APG5EVTL0x40CPG5EVTH0x40EPG5FPCIL0x410PG5FPCIH0x412PG5CLPCIL0x414PG5CLPCIH0x416PG5FFPCIL0x418PG5FFPCIH0x41APG5SPCIL0x41CPG5SPCIH0x41EPG5LEBL0x420PG5LEBH0x422PG5PHASE0x424PG5DC0x426PG5DCA0x428PG5PER0x42APG5TRIGA0x42CPG5TRIGB0x42EPG5TRIGC0x430PG5DTL0x432PG5DTH0x434PG5CAP0x436PG6CONL0x438PG6CONH0x43APG6STAT0x43CPG6IOCONL0x43EPG6IOCONH0x440PG6EVTL0x442PG6EVTH0x444PG6FPCIL0x446PG6FPCIH0x448PG6CLPCIL0x44APG6CLPCIH0x44CPG6FFPCIL0x44EPG6FFPCIH0x450PG6SPCIL0x452PG6SPCIH0x454PG6LEBL0x456PG6LEBH0x458PG6PHASE0x45APG6DC0x45CPG6DCA0x45EPG6PER0x460PG6TRIGA0x462PG6TRIGB0x464PG6TRIGC0x466PG6DTL0x468PG6DTH0x46APG6CAP0x46CPG7CONL0x46EPG7CONH0x470PG7STAT0x472PG7IOCONL0x474PG7IOCONH0x476PG7EVTL0x478PG7EVTH0x47APG7FPCIL0x47CPG7FPCIH0x47EPG7CLPCIL0x480PG7CLPCIH0x482PG7FFPCIL0x484PG7FFPCIH0x486PG7SPCIL0x488PG7SPCIH0x48APG7LEBL0x48CPG7LEBH0x48EPG7PHASE0x490PG7DC0x492PG7DCA0x494PG7PER0x496PG7TRIGA0x498PG7TRIGB0x49APG7TRIGC0x49CPG7DTL0x49EPG7DTH0x4A0PG7CAP0x4A2PG8CONL0x4A4PG8CONH0x4A6PG8STAT0x4A8PG8IOCONL0x4AAPG8IOCONH0x4ACPG8EVTL0x4AEPG8EVTH0x4B0PG8FPCIL0x4B2PG8FPCIH0x4B4PG8CLPCIL0x4B6PG8CLPCIH0x4B8PG8FFPCIL0x4BAPG8FFPCIH0x4BCPG8SPCIL0x4BEPG8SPCIH0x4C0PG8LEBL0x4C2PG8LEBH0x4C4PG8PHASE0x4C6PG8DC0x4C8PG8DCA0x4CAPG8PER0x4CCPG8TRIGA0x4CEPG8TRIGB0x4D0PG8TRIGC0x4D2PG8DTL0x4D4PG8DTH0x4D6PG8CAP0x4D8

Pins