dsPIC33CK32MC103 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x005F00), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0x5F00 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table bit Enabled AIVT Disabled AIVT CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0x5F10 0xFFFFFF default 0xFFFFFF BSLIM Boot Segment Flash Page Address Limit bits FSIGN · 0x5F14 0xFF7FFF default 0xFF7FFF FSIGN Sign Bit Configuration FOSCSEL · 0x5F18 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Low-Power RC Oscillator (LPRC) Back up Fast RC (BFRC) Oscillator Internal Fast RC (FRC) Oscillator with postscaler FOSC · 0x5F1C 0xFFFFFF default 0xFFFFFF XTBST XT Boost Default kick-start Boost the kick-start XTCFG XT Config 4-8 MHz crystals 8-16 MHz crystals 16-24 MHz crystals 24-32 MHz crystals PLLKEN PLL Lock Enable PLL clock output will not be disabled if LOCK is lost PLL clock output will be disabled if LOCK is lost FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) OSCIOFNC OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select bits EC (External Clock) Mode XT Crystal Oscillator Mode HS Crystal Oscillator Mode Primary Oscillator disabled FWDT · 0x5F20 0xFFFFFF default 0xFFFFFF FWDTEN Watchdog Timer Enable bit WDT controlled via SW, use WDTCON.ON bit WDT enabled in hardware SWDTPS Sleep Mode Watchdog Timer Post Scaler select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 1:2097152 1:4194304 1:8388608 1:16777216 1:33554432 1:67108864 1:134217728 1:268435456 1:536870912 1:1073741824 1:2147483648 WDTWIN Watchdog Timer Window Select bits WDT Windo is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period WINDIS Watchdog Timer Window Enable bit Watchdog Timer operates in Window mode Watchdog Timer operates in Non-Window mode RCLKSEL Watchdog Timer Clock Select bits Use peripheral clk when system clock is not INTOSC/LPRC and device is not in Sleep;otherwise, use INTOSC/LPRC Use FRC when WINDIS = 0, system clock is not INTOSC/LPRC and device is not in Sleep;otherwise, use INTOSC/LPRC Always use LPRC RWDTPS Run Mode Watchdog Timer Post Scaler select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 1:2097152 1:4194304 1:8388608 1:16777216 1:33554432 1:67108864 1:134217728 1:268435456 1:536870912 1:1073741824 1:2147483648 FPOR · 0x5F24 0xFFFFFF default 0xFFFFFF BISTDIS Memory BIST Feature Disable mBIST on reset feature enabled mBIST on reset feature disabled FICD · 0x5F28 0xFFFFDF default 0xFFFFDF JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGC3 and PGD3 Communicate on PGC2 and PGD2 Communicate on PGC1 and PGD1 FDMTIVTL · 0x5F2C 0xFFFFFF default 0xFFFFFF DMTIVTL Dead Man Timer Interval low word FDMTIVTH · 0x5F30 0xFFFFFF default 0xFFFFFF DMTIVTH Dead Man Timer Interval high word FDMTCNTL · 0x5F34 0xFFFFFF default 0xFFFFFF DMTCNTL Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) FDMTCNTH · 0x5F38 0xFFFFFF default 0xFFFFFF DMTCNTH Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) FDMT · 0x5F3C 0xFFFFFF default 0xFFFFFF DMTDIS Dead Man Timer Disable bit Dead Man Timer is Enabled and cannot be disabled by software Dead Man Timer is Disabled and can be enabled by software FDEVOPT · 0x5F40 0xFFFCFF default 0xFFFCFF SPI2PIN SPI2 Pin Select bit SPI2 uses dedicated I/O pins SPI2 uses I/O remap (PPS) pins SMB3EN SM Bus Enable Normal SMBus input levels SMBus 3.0 input levels ALTI2C1 Alternate I2C1 Pin bit I2C1 mapped to ASDA1/ASCL1 pins I2C1 mapped to SDA1/SCL1 pins FALTREG · 0x5F44 0xFFFFFF default 0xFFFFFF CTXT4 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT3 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT2 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT1 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned 
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