dsPIC33EP64GS805 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x00AF80), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0xAF80 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table bit Enabled AIVT Disabled AIVT CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0xAF90 0x001FFF default 0x001FFF BSLIM Boot Segment Flash Page Address Limit bits FSIGN · 0xAF94 0xFF7FFF default 0xFF7FFF SIGN Sign Bit FOSCSEL · 0xAF98 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Low-Power RC Oscillator (LPRC) Fast RC Oscillator with divide-by-16 Internal Fast RC (FRC) Oscillator with postscaler FOSC · 0xAF9C 0xFFFFFF default 0xFFFFFF PLLKEN PLL Lock Enable Bit Clock switch will not wait for the PLL lock signal Clock switch to PLL source will wait until the PLL lock signal is valid FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral pin select configuration bit Allow multiple reconfigurations Allow only one reconfiguration OSCIOFNC OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select bits EC (External Clock) Mode XT Crystal Oscillator Mode HS Crystal Oscillator Mode Primary Oscillator disabled FWDT · 0xAFA0 0xFFFFFF default 0xFFFFFF WDTWIN Watchdog Timer Window Select bits WDT Windo is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period WINDIS Watchdog Timer Window Enable bit Watchdog Timer in Window mode Watchdog Timer in Non-Window mode WDTEN Watchdog Timer Enable bits WDT and SWDTEN disabled WDT Enabled only while device is active (disabled in sleep, SWDTEN disabled) WDT Enabled/Disabled (controlled using SWDTEN bit) WDT Enabled WDTPRE Watchdog Timer Prescaler bit 1:32 1:128 WDTPOST Watchdog Timer Postscaler bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xAFA4 0xFFFFFF default 0xFFFFFF BOREN Brown Out Enable bit Brown Out Disabled Brown Out Enable Bit FICD · 0xAFA8 0xFFFFDF default 0xFFFFDF BTSWP BOOTSWP Instruction Enable/Disable bit BOOTSWP instruction is enabled BOOTSWP instruction is disabled BACKBUG Background Debug Enabled Disabled JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGEC3 and PGED3 Communicate on PGEC2 and PGED2 Communicate on PGEC1 and PGED1 FDEVOPT · 0xAFAC 0xFFFFFF default 0xFFFFFF DBCC DACx Output Cross Connection bit Interconnects DACOUT1 and DACOUT2 No Cross Connection between DAC outputs ALTI2C2 Alternate I2C2 Pin bit I2C2 mapped to ASDA2/ASCL2 pins I2C2 mapped to SDA2/SCL2 pins ALTI2C1 Alternate I2C1 Pin bit I2C1 mapped to ASDA1/ASCL1 pins I2C1 mapped to SDA1/SCL1 pins PWMLOCK PWMx Lock Enable bit PWM registers may be written without key sequence Certain PWM registers may only be written after key sequency FALTREG · 0xAFB0 0xFFFFFF default 0xFFFFFF CTXT4 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT3 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT2 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned CTXT1 Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits Alternate Register set assigned to IPL level 1 Alternate Register set assigned to IPL level 2 Alternate Register set assigned to IPL level 3 Alternate Register set assigned to IPL level 4 Alternate Register set assigned to IPL level 5 Alternate Register set assigned to IPL level 6 Alternate Register set assigned to IPL level 7 Not Assigned FBTSEQ · 0xAFFC 0x000FFF default 0x000FFF IBSEQ The one's complement of BSEQ; must be calculated by the user and written during device programming. BSEQ Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active 
BETA