dsPIC33EV64GM103 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x00AB80), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0xAB80 0xFFFF default 0xFFFF AIVTDIS Alternate Interrupt Vector Table Disable Bit Enable Alternate Vector Table Disable Alternate Vector Table CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect Bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect Bit General Segment is write protected General Segment may be written BSS2 Boot Segment Control Bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect Bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0xAB90 0xFFFF default 0xFFFF BSLIM Boot Segment Code Flash Page Address Limit Bits FSIGN · 0xAB94 0x7FFF default 0x7FFF FSIGN FOSCSEL · 0xAB98 0xFFFF default 0xFFFF IESO Two Speed Oscillator Start-Up Bit Start up device with user selected oscillator source Start up device with FRC,then automatically switch to user selected oscillator source FNOSC Initial oscillator Source Selection Bits Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Low-Power RC Oscillator (LPRC) Internal Fast RC (FRC) Oscillator with divide by 16 Internal Fast RC (FRC) Oscillator with postscaler FOSC · 0xAB9C 0xFFFF default 0xFFFF PLLKEN PLL Lock Enable Bit Clock switch will not wait for the PLL lock signal Clock switch to PLL source will wait until the PLL lock signal is valid FCKSM Clock Switching Mode Bits Both Clock Switching and Fail-safe Clock Monitor are enabled Clock Switching is enabled,Fail-safe Clock Monitor is disabled Both Clock Switching and Fail-safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral Pin Select Configuration Bit Allow Multiple reconfigurations Allow Only One reconfiguration OSCIOFNC OSC2 Pin I/O Function Enable Bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select Bits EC (External Clock) mode XT Crystal Oscillator mode HS Crystal Oscillator mode Primary Oscillator disabled FWDT · 0xABA0 0xFFFF default 0xFFFF WDTWIN Watchdog Window Select Bits WDT Window is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period WINDIS Watchdog Timer Window Enable Bit Watchdog timer in Window Mode Watchdog timer in Non-Window Mode FWDTEN Watchdog Timer Enable Bits WDT and SWDTEN Disabled WDT Enabled only while device is active (disabled in sleep, SWDTEN disabled) WDT Enabled/Disabled (controlled using SWDTEN bit) WDT Enabled WDTPRE Watchdog Timer Prescaler Bit 1:32 1:128 WDTPOST Watchdog Timer Postscaler Bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xABA4 0xFFFF default 0xFFFF BOREN0 Brown Out Reset Detection Bit BOR is Disabled BOR is Enabled FICD · 0xABA8 0xFFFF default 0xFFFF ICS ICD Communication Channel Select Bits Reserved, do not use Communicate on PGEC3 and PGED3 Communicate on PGEC2 and PGED2 Communicate on PGEC1 and PGED1 FDMTINTVL · 0xABAC 0xFFFF default 0xFFFF DMTIVTL Lower 16 Bits of 32 Bit DMT Window Interval FDMTINTVH · 0xABB0 0xFFFF default 0xFFFF DMTIVTH Upper 16 Bits of 32 Bit DMT Window Interval FDMTCNTL · 0xABB4 0xFFFF default 0xFFFF DMTCNTL Lower 16 Bits of 32 Bit DMT Instruction Count Time-Out Value FDMTCNTH · 0xABB8 0xFFFF default 0xFFFF DMTCNTH Upper 16 Bits of 32 Bit DMT Instruction Count Time-Out Value FDMT · 0xABBC 0xFFFF default 0xFFFF DMTEN Dead Man Timer Enable Bit Dead Man Timer is Disabled and can be enabled by software Dead Man Timer is Enabled and cannot be disabled by software FDEVOPT · 0xABC0 0xFFFF default 0xFFFF ALTI2C1 Alternate I2C1 Pins Selection Bit I2C1 mapped to ASDA1/ASCL1 pins I2C1 mapped to SDA1/SCL1 pins PWMLOCK PWM Lock Enable Bit PWM registers may be written without key sequence Certain PWM registers may only be written after key sequence FALTREG · 0xABC4 0xFFFF default 0xFFFF CTXT2 Interrupt Priority Level (IPL) Selection Bits For Alternate Working Register Set 2 Alternate register set 2 assigned to IPL level 1 Alternate register set 2 assigned to IPL level 2 Alternate register set 2 assigned to IPL level 3 Alternate register set 2 assigned to IPL level 4 Alternate register set 2 assigned to IPL level 5 Alternate register set 2 assigned to IPL level 6 Alternate register set 2 assigned to IPL level 7 Not Assigned CTXT1 Interrupt Priority Level (IPL) Selection Bits For Alternate Working Register Set 1 Alternate register set 1 assigned to IPL level 1 Alternate register set 1 assigned to IPL level 2 Alternate register set 1 assigned to IPL level 3 Alternate register set 1 assigned to IPL level 4 Alternate register set 1 assigned to IPL level 5 Alternate register set 1 assigned to IPL level 6 Alternate register set 1 assigned to IPL level 7 Not Assigned 
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