dsPIC33FJ12MC201 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FBS · 0xF80000 0x000F default 0x000F BSS Boot Segment Program Flash Code Protection High Security, Large-sized Boot Flash High Security, Large-sized Boot Flash High Security, Medium-sized Boot Flash High Security, Medium-sized Boot Flash High Security, Small-sized Boot Flash High Security, Small-sized Boot Flash Standard Security, Large-sized Boot Flash Standard Security, Large-sized Boot Flash Standard Security, Medium-sized Boot Flash Standard Security, Medium-sized Boot Flash Standard Security, Small-sized Boot Flash Standard Security, Small-sized Boot Flash No Boot program Flash segment No Boot program Flash segment BWRP Boot Segment Write Protect Boot segment is write-protected Boot Segment may be written FGS · 0xF80004 0x0007 default 0x0007 GSS General Segment Code Protection High Security Code Protection is Enabled Standard Security Code Protection is Enabled User program memory is not code-protected GWRP General Code Segment Write Protect User program memory is write-protected User program memory is not write-protected FOSCSEL · 0xF80006 0x0087 default 0x0087 IESO Internal External Switch Over Mode Start-up device with user-selected oscillator source Start-up device with FRC, then automatically switch to user-selected oscillator source when ready FNOSC Oscillator Mode Internal Fast RC (FRC) Internal Fast RC (FRC) w/ PLL Primary Oscillator (XT, HS, EC) Primary Oscillator (XT, HS, EC) w/ PLL Secondary Oscillator (SOSC) Low Power RC Oscillator (LPRC) Internal Fast RC (FRC) divide by 16 Internal Fast RC (FRC) with divide by N FOSC · 0xF80008 0x00E7 default 0x00E7 FCKSM Clock Switching and Monitor Both Clock Switching and Fail-Safe Clock Monitor are enabled Clock switching is enabled, Fail-Safe Clock Monitor is disabled Both Clock Switching and Fail-Safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral Pin Select Configuration Allow Multiple Re-configurations Allow Only One Re-configuration OSCIOFNC OSC2 Pin Function OSC2 pin has digital I/O function OSC2 pin has clock out function POSCMD Primary Oscillator Source EC Oscillator Mode XT Oscillator Mode HS Oscillator Mode Primary Oscillator Disabled FWDT · 0xF8000A 0x00DF default 0x00DF FWDTEN Watchdog Timer Enable Watchdog timer enabled/disabled by user software Watchdog timer always enabled WINDIS Watchdog Timer Window Watchdog Timer in Window mode Watchdog Timer in Non-Window mode WDTPRE WDT Prescaler 1:32 1:128 WDTPOST Watchdog Timer Postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xF8000C 0x00F7 default 0x00F7 PWMPIN Motor Control PWM Module Pin Mode bit PWM module pins controlled by PWM module at device Reset PWM module pins controlled by PORT register at device Reset HPOL Motor Control PWM High Side Polarity bit PWM module high side output pins have active-low output polarity PWM module high side output pins have active-high output polarity LPOL Motor Control PWM Low Side Polarity bit PWM module low side output pins have active-low output polarity PWM module low side output pins have active-high output polarity ALTI2C Alternate I2C pins I2C mapped to ASDA1/ASCL1 pins I2C mapped to SDA1/SCL1 pins FPWRT POR Timer Value Disabled 2ms 4ms 8ms 16ms 32ms 64ms 128ms FICD · 0xF8000E 0xFFDF default 0xFFDF BACKBUG Background Debug Enabled Disabled COE Set Clip On Emulation Mode Reset Into Clip On Emulation Mode Reset Into Operational Mode JTAGEN JTAG Port Enable JTAG is Disabled JTAG is Enabled ICS Comm Channel Select Communicate on PGC3/EMUC3 and PGD3/EMUD3 Communicate on PGC2/EMUC2 and PGD2/EMUD2 Communicate on PGC1/EMUC1 and PGD1/EMUD1 
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