PIC16CR62 registers All 30 registers by peripheral, at their data-memory address as the register file map gives it (bank and offset), with their reset value and every bit.
CPU CPU core INDF
Address 0x00
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – PCL
Address 0x02
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – 7 IRP 6 RP1 5 RP0 4 nTO 3 nPD 2 Z 1 DC 0 C 7 fields
Field Bits What it does IRP 7 RP 6:5 nTO 4 nPD 3 Z 2 DC 1 C 0
7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – PCLATH
Address 0x0A
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – TMR0 Timer0 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – OPTION_REG
Address 0x81
Reset 0xFF
Access read/write 7 nRBPU 6 INTEDG 5 T0CS 4 T0SE 3 PSA 2 PS2 1 PS1 0 PS0 6 fields
Field Bits What it does nRBPU 7 INTEDG 6 T0CS 5 T0SE 4 PSA 3 PS 2:0
PORTA I/O port A 7 – 6 – 5 RA5 4 RA4 3 RA3 2 RA2 1 RA1 0 RA0 6 fields
Field Bits What it does RA5 5 RA4 4 RA3 3 RA2 2 RA1 1 RA0 0
TRISA
Address 0x85
Reset 0x3F
Access read/write 7 – 6 – 5 TRISA5 4 TRISA4 3 TRISA3 2 TRISA2 1 TRISA1 0 TRISA0 6 fields
Field Bits What it does TRISA5 5 TRISA4 4 TRISA3 3 TRISA2 2 TRISA1 1 TRISA0 0
PORTB I/O port B 7 RB7 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 8 fields
Field Bits What it does RB7 7 RB6 6 RB5 5 RB4 4 RB3 3 RB2 2 RB1 1 RB0 0
TRISB
Address 0x86
Reset 0xFF
Access read/write 7 TRISB7 6 TRISB6 5 TRISB5 4 TRISB4 3 TRISB3 2 TRISB2 1 TRISB1 0 TRISB0 8 fields
Field Bits What it does TRISB7 7 TRISB6 6 TRISB5 5 TRISB4 4 TRISB3 3 TRISB2 2 TRISB1 1 TRISB0 0
PORTC I/O port C 7 RC7 6 RC6 5 RC5 4 RC4 3 RC3 2 RC2 1 RC1 0 RC0 8 fields
Field Bits What it does RC7 7 RC6 6 RC5 5 RC4 4 RC3 3 RC2 2 RC1 1 RC0 0
TRISC
Address 0x87
Reset 0xFF
Access read/write 7 TRISC7 6 TRISC6 5 TRISC5 4 TRISC4 3 TRISC3 2 TRISC2 1 TRISC1 0 TRISC0 8 fields
Field Bits What it does TRISC7 7 TRISC6 6 TRISC5 5 TRISC4 4 TRISC3 3 TRISC2 2 TRISC1 1 TRISC0 0
INTERRUPT Interrupts 7 GIE 6 PEIE 5 T0IE 4 INTE 3 RBIE 2 T0IF 1 INTF 0 RBIF 8 fields
Field Bits What it does GIE 7 PEIE 6 T0IE 5 INTE 4 RBIE 3 T0IF 2 INTF 1 RBIF 0
PIR1
Address 0x0C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 SSPIF 2 CCP1IF 1 TMR2IF 0 TMR1IF 4 fields
Field Bits What it does SSPIF 3 CCP1IF 2 TMR2IF 1 TMR1IF 0
PIE1
Address 0x8C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 SSPIE 2 CCP1IE 1 TMR2IE 0 TMR1IE 4 fields
Field Bits What it does SSPIE 3 CCP1IE 2 TMR2IE 1 TMR1IE 0
TMR1 Timer1 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – T1CON
Address 0x10
Reset 0x00
Access read/write 7 – 6 – 5 T1CKPS1 4 T1CKPS0 3 T1OSCEN 2 nT1SYNC 1 TMR1CS 0 TMR1ON 5 fields
Field Bits What it does T1CKPS 5:4 T1OSCEN 3 nT1SYNC 2 TMR1CS 1 TMR1ON 0
TMR2 Timer2 TMR2
Address 0x11
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – T2CON
Address 0x12
Reset 0x00
Access read/write 7 – 6 TOUTPS3 5 TOUTPS2 4 TOUTPS1 3 TOUTPS0 2 TMR2ON 1 T2CKPS1 0 T2CKPS0 3 fields
Field Bits What it does TOUTPS 6:3 TMR2ON 2 T2CKPS 1:0
PR2
Address 0x92
Reset 0xFF
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – MSSP Master synchronous serial port (SPI, I²C) 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – SSPCON
Address 0x14
Reset 0x00
Access read/write 7 WCOL 6 SSPOV 5 SSPEN 4 CKP 3 SSPM3 2 SSPM2 1 SSPM1 0 SSPM0 5 fields
Field Bits What it does WCOL 7 SSPOV 6 SSPEN 5 CKP 4 SSPM 3:0
SSPADD
Address 0x93
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – SSPSTAT
Address 0x94
Reset 0x00
Access read/write 7 – 6 – 5 D/nA 4 P 3 S 2 R/nW 1 UA 0 BF 6 fields
Field Bits What it does D/nA 5 P 4 S 3 R/nW 2 UA 1 BF 0
CCP1 Capture/compare/PWM 1 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – CCP1CON
Address 0x17
Reset 0x00
Access read/write 7 – 6 – 5 DC1B1 4 DC1B0 3 CCP1M3 2 CCP1M2 1 CCP1M1 0 CCP1M0 2 fields
Field Bits What it does DC1B 5:4 CCP1M 3:0
OSCILLATOR Oscillator, power control and watchdog 7 – 6 – 5 – 4 – 3 – 2 – 1 nPOR 0 nBOR 2 fields
Field Bits What it does nPOR 1 nBOR 0
BETA