PIC16F1455 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1 · 0x8007 0x3FFF default 0x3FFF FCMEN Fail-Safe Clock Monitor Enable Fail-Safe Clock Monitor is disabled Fail-Safe Clock Monitor is enabled IESO Internal/External Switchover Mode Internal/External Switchover Mode is disabled Internal/External Switchover Mode is enabled CLKOUTEN Clock Out Enable CLKOUT function is enabled on the CLKOUT pin CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin BOREN Brown-out Reset Enable Brown-out Reset disabled Brown-out Reset controlled by the SBOREN bit in the BORCON register Brown-out Reset enabled while running and disabled in Sleep Brown-out Reset enabled CP Flash Program Memory Code Protection Program memory code protection is enabled Program memory code protection is disabled MCLRE MCLR Pin Function Select MCLR/VPP pin function is digital input MCLR/VPP pin function is MCLR PWRTE Power-up Timer Enable PWRT enabled PWRT disabled WDTE Watchdog Timer Enable WDT disabled WDT controlled by the SWDTEN bit in the WDTCON register WDT enabled while running and disabled in Sleep WDT enabled FOSC Oscillator Selection Bits LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins EXTRC oscillator: External RC circuit connected to CLKIN pin INTOSC oscillator: I/O function on CLKIN pin ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins CONFIG2 · 0x8008 0x3FFF default 0x3FFF LVP Low-Voltage Programming Enable High-voltage on MCLR/VPP must be used for programming Low-voltage programming enabled LPBOR Low-Power Brown Out Reset Low-Power BOR is enabled Low-Power BOR is disabled BORV Brown-out Reset Voltage Selection Brown-out Reset Voltage (Vbor), high trip point selected. Brown-out Reset Voltage (Vbor), low trip point selected. STVREN Stack Overflow/Underflow Reset Enable Stack Overflow or Underflow will not cause a Reset Stack Overflow or Underflow will cause a Reset PLLEN PLL Enable Bit 3x or 4x PLL Disabled 3x or 4x PLL Enabled PLLMULT PLL Multiplier Selection Bit 4x Output Frequency Selected 3x Output Frequency Selected USBLSCLK USB Low Speed Clock Selection bit System clock expects 24 MHz, FS/LS USB CLKENs divide-by is set to 4. System clock expects 48 MHz, FS/LS USB CLKENs divide-by is set to 8. CPUDIV CPU System Clock Selection Bit NO CPU system divide CPU system clock divided by 2 CPU system clock divided by 3 CPU system clock divided by 6 WRT Flash Memory Self-Write Protection 000h to 1FFFh write protected, no addresses may be modified by PMCON control 000h to 0FFFh write protected, 1000h to 1FFFh may be modified by PMCON control 000h to 1FFh write protected, 200h to 1FFFh may be modified by PMCON control Write protection off 
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