PIC16F1578 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1 · 0x8007 0x3FFF default 0x3FFF CLKOUTEN Clock Out Enable CLKOUT function is enabled on the CLKOUT pin CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin BOREN Brown-out Reset Enable Brown-out Reset disabled Brown-out Reset controlled by the SBOREN bit in the BORCON register Brown-out Reset enabled while running and disabled in Sleep Brown-out Reset enabled CP Flash Program Memory Code Protection Program memory code protection is enabled Program memory code protection is disabled MCLRE MCLR Pin Function Select MCLR/VPP pin function is digital input MCLR/VPP pin function is MCLR PWRTE Power-up Timer Enable PWRT enabled PWRT disabled WDTE Watchdog Timer Enable WDT disabled WDT controlled by the SWDTEN bit in the WDTCON register WDT enabled while running and disabled in Sleep WDT enabled FOSC Oscillator Selection Bits INTOSC oscillator; I/O function on CLKIN pin ECL, External Clock, Low Power Mode (0-0.5 MHz); device clock supplied to CLKIN pin ECM, External Clock, Medium Power Mode (0.5-4 MHz); device clock supplied to CLKIN pin ECH, External Clock, High Power Mode (4-32 MHz); device clock supplied to CLKIN pin CONFIG2 · 0x8008 0x3FFF default 0x3FFF LVP Low-Voltage Programming Enable High-voltage on MCLR/VPP must be used for programming Low-voltage programming enabled DEBUG In-Circuit Debugger Mode In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins LPBOREN Low Power Brown-out Reset enable bit LPBOR is enabled LPBOR is disabled BORV Brown-out Reset Voltage Selection Brown-out Reset Voltage (Vbor), high trip point selected. Brown-out Reset Voltage (Vbor), low trip point selected. STVREN Stack Overflow/Underflow Reset Enable Stack Overflow or Underflow will not cause a Reset Stack Overflow or Underflow will cause a Reset PLLEN PLL Enable 4x PLL disabled 4x PLL enabled PPS1WAY PPSLOCK bit One-Way Set Enable bit PPSLOCKED Bit Can Be Cleared & Set Repeatedly PPSLOCKED Bit Can Be Cleared & Set Once WRT Flash Memory Self-Write Protection 000h to FFFh write protected, no addresses may be modified by EECON control 000h to 7FFh write protected, 800h to FFFh may be modified by EECON control 000h to 1FFh write protected, 200h to FFFh may be modified by EECON control Write protection off 
BETA