PIC16F17145 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1 · 0x8007 0x3FFF default 0x3FFF FCMEN Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled VDDAR VDD Range Analog Calibration Selection bit Internal analog systems are calibrated for operation between VDD = 1.8 - 3.6V Internal analog systems are calibrated for operation between VDD = 2.3 - 5.5V CSWEN Clock Switch Enable bit The NOSC and NDIV bits cannot be changed by user software Writing to NOSC and NDIV is allowed CLKOUTEN Clock Out Enable bit CLKOUT function is enabled; FOSC/4 clock appears at OSC2 CLKOUT function is disabled; i/o or oscillator function on OSC2 RSTOSC Reset Oscillator Selection bits HFINTOSC (32 MHz) HFINTOSC (16 MHz) EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits SOSC LFINTOSC HFINTOSC (1MHz) EXTOSC operating per FEXTOSC bits FEXTOSC External Oscillator Selection bits LP (crystal oscillator) optimized for 32.768kHz XT (crystal oscillator) above 100kHz, below 4MHz HS (crystal oscillator) above 4MHz Oscillator not enabled EC (external clock) below 16 MHz EC (external clock) above 16 MHz CONFIG2 · 0x8008 0x3FFF default 0x3FFF DEBUG Background Debugger background debugger enabled Background Debugger disabled STVREN Stack Overflow/Underflow Reset Enable bit Stack Overflow or Underflow will not cause a reset Stack Overflow or Underflow will cause a reset PPS1WAY PPSLOCKED One-Way Set Enable bit The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required) The PPSLOCKED bit can be cleared and set only once after an unlocking sequence is executed; once PPSLOCKED is set, all future changes to PPS registers are prevented ZCD ZCD Disable bit ZCD module is always enabled; ZCDMD and ZCDSEN bits are ignored ZCD module is disabled; ZCD can be enabled by setting the ZCDSEN bit of ZCDCON BORV Brown-out Reset Voltage Selection bit Brown-out Reset Voltage (VBOR) is set to 2.85V Brown-out Reset Voltage (VBOR) set to 1.9V DACAUTOEN DAC Buffer Automatic Range Select Enable bit DAC Buffer reference range is automatically determined by module hardware DAC Buffer reference range is determined by the REFRNG bit BOREN Brown-out Reset Enable bits Brown-out reset disabled Brown-out reset enabled according to SBOREN bit Brown-out Reset enabled while running, disabled in sleep; SBOREN is ignored Brown-out Reset enabled, SBOREN bit is ignored LPBOREN Low-Power BOR Enable bit ULPBOR enabled ULPBOR disabled PWRTS Power-up Timer Selection bits PWRT set at 1 ms PWRT set at 16 ms PWRT set at 64 ms PWRT is disabled MCLRE Master Clear Enable bit If LVP = 0, MCLR is port-defined function; If LVP = 1, RA3 pin function is MCLR If LVP = 0, MCLR pin is MCLR; If LVP = 1, RA3 pin function is MCLR CONFIG3 · 0x8009 0x3FFF default 0x3FFF WDTCCS WDT Input Clock Select bits WDT reference clock is the 31.0 kHz LFINTOSC WDT reference clock is the 32 kHz MFINTOSC WDT reference clock is the 32kHz secondary oscillator Software Control WDTCWS WDT Window Select bits window delay = 87.5 percent of time; no software control; keyed access required window delay = 75 percent of time; no software control; keyed access required window delay = 62.5 percent of time; no software control; keyed access required window delay = 50 percent of time; no software control; keyed access required window delay = 37.5 percent of time; no software control; keyed access required window delay = 25 percent of time; no software control; keyed access required window always open (100%); no software control; keyed access required window always open (100%); software control; keyed access not required WDTE WDT Operating Mode bits WDT Disabled, SEN is ignored WDT enabled/disabled by SEN bit WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN is ignored WDT enabled regardless of Sleep; SEN bit is ignored WDTCPS WDT Period Select bits Divider ratio 1:32 Divider ratio 1:64 Divider ratio 1:128 Divider ratio 1:256 Divider ratio 1:512 Divider ratio 1:1024 Divider ratio 1:2048 Divider ratio 1:4096 Divider ratio 1:8192 Divider ratio 1:16384 Divider ratio 1:32768 Divider ratio 1:65536 Divider ratio 1:131072 Divider ratio 1:262144 Divider ratio 1:524299 Divider ratio 1:1048576 Divider ratio 1:2097152 Divider ratio 1:4194304 Divider ratio 1:8388608 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:65536; software control of WDTPS CONFIG4 · 0x800A 0x3FFF default 0x3FFF LVP Low Voltage Programming Enable bit High Voltage on MCLR/Vpp must be used for programming Low Voltage programming enabled. MCLR/Vpp pin function is MCLR. MCLRE Configuration bit is ignored WRTSAF Storage Area Flash (SAF) Write Protection bit SAF is write protected SAF is NOT write protected WRTD Data EEPROM Write Protection bit Data EEPROM is write protected Data EEPROM is NOT write protected WRTC Configuration Register Write Protection bit Configuration Register is write protected Configuration Register is NOT write protected WRTB Boot Block Write Protection bit Boot Block is write protected Boot Block is NOT write protected WRTAPP Application Block Write Protection bit Application Block is write protected Application Block is NOT write protected SAFEN Storage Area Flash (SAF) Enable bit SAF enabled SAF disabled BBEN Boot Block Enable bit Boot Block enabled Boot Block disabled BBSIZE Boot Block Size Selection bits * half of user program memory * half of user program memory * half of user program memory * half of user program memory 4096 word boot block size 2048 words boot block size 1024 words boot block size 512 words boot block size CONFIG5 · 0x800B 0x3FFF default 0x3FFF CPD Data EEPROM Code Protection bit Data EEPROM code protection is enabled Data EEPROM code protection is disabled CP Program Flash Memory Code Protection bit Program Flash Memory code protection is enabled Program Flash Memory code protection is disabled 
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