PIC16F18313 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1 · 0x8007 0x3FFF default 0x3FFF FCMEN Fail-Safe Clock Monitor Enable Fail-Safe Clock Monitor is disabled Fail-Safe Clock Monitor is enabled CSWEN Clock Switch Enable bit The NOSC and NDIV bits cannot be changed by user software Writing to NOSC and NDIV is allowed CLKOUTEN Clock Out Enable bit CLKOUT function is enabled; FOSC/4 clock appears at OSC2 CLKOUT function is disabled; I/O or oscillator function on OSC2 RSTOSC Power-up default value for COSC bits HFINTOSC with 2x PLL (32MHz) EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits Reserved SOSC (31kHz) LFINTOSC (31kHz) Unimplemented HFINTOSC (1MHz) EXTOSC operating per FEXTOSC bits FEXTOSC FEXTOSC External Oscillator mode Selection bits LP (crystal oscillator) optimized for 32.768 kHz XT (crystal oscillator) from 100 kHz to 4 MHz HS (crystal oscillator) above 4 MHz Unimplemented Oscillator not enabled EC (external clock) below 100 kHz EC (external clock) for 100 kHz to 8 MHz EC (external clock) above 8 MHz CONFIG2 · 0x8008 0x3FFF default 0x3FFF DEBUG Debugger enable bit Background debugger enabled Background debugger disabled STVREN Stack Overflow/Underflow Reset Enable bit Stack Overflow or Underflow will not cause a Reset Stack Overflow or Underflow will cause a Reset PPS1WAY PPSLOCK bit One-Way Set Enable bit The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle BORV Brown-out Reset Voltage selection bit Brown-out voltage (Vbor) set to 2.7V Brown-out voltage (Vbor) set to 2.45V BOREN Brown-out Reset Enable bits Brown-out Reset disabled Brown-out Reset enabled according to SBOREN Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored Brown-out Reset enabled, SBOREN bit ignored LPBOREN Low-power BOR enable bit ULPBOR enabled ULPBOR disabled WDTE Watchdog Timer Enable bits WDT disabled; SWDTEN is ignored WDT controlled by the SWDTEN bit in the WDTCON register WDT enabled while running and disabled while in SLEEP/IDLE; SWDTEN is ignored WDT enabled, SWDTEN is ignored PWRTE Power-up Timer Enable bit PWRT enabled PWRT disabled MCLRE Master Clear Enable bit MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit. MCLR/VPP pin function is MCLR; Weak pull-up enabled CONFIG3 · 0x8009 0x3FFF default 0x3FFF LVP Low Voltage Programming Enable bit HV on MCLR/VPP must be used for programming. Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored. WRT User NVM self-write protection bits 0000h to 07FFh write protected, no addresses may be modified 0000h to 03FFh write-protected, 0400h to 07FFh may be modified 0000h to 01FFh write-protected, 0200h to 07FFh may be modified Write protection off CONFIG4 · 0x800A 0x3FFF default 0x3FFF CPD Data NVM Memory Code Protection bit Data NVM code protection enabled Data NVM code protection disabled CP User NVM Program Memory Code Protection bit User NVM code protection enabled User NVM code protection disabled 
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