BETAPIC18F05Q40 interrupt vectors
Reset at 0x0000, then a vector table of 78 sources: each source's entry is at IVTBASE + 2 × its IRQ number (IVTBASE is 0x0008 after reset) and holds its handler's address. With MVECEN off the chip uses 0x0008 and 0x0018 as the other PIC18s do. Each source has an enable bit and a flag (the Registers page lists them). In XC8 a handler is void __interrupt(irq(TMR0)) isr(void).
| Vector | Program address | Name | Handler | Source |
|---|---|---|---|---|
| 0 | 0x0000 | RESET | reset: main() after start-up | Reset vector, address 0x0000 |
| 1 | 0x0008 | SWINT | __interrupt(irq(SWINT)) | Software Interrupt; IRQ 0, vector table entry IVTBASE + 0x00 (IVTBASE resets to 0x0008) |
| 2 | 0x000A | HLVD | __interrupt(irq(HLVD)) | HLVD Interrupt; IRQ 1, vector table entry IVTBASE + 0x02 (IVTBASE resets to 0x0008) |
| 3 | 0x000C | OSF | __interrupt(irq(OSF)) | Oscillator Failure Interrupt; IRQ 2, vector table entry IVTBASE + 0x04 (IVTBASE resets to 0x0008) |
| 4 | 0x000E | CSW | __interrupt(irq(CSW)) | Clock Switch Interrupt; IRQ 3, vector table entry IVTBASE + 0x06 (IVTBASE resets to 0x0008) |
| 5 | 0x0010 | NVMIP | __interrupt(irq(NVMIP)) | ; IRQ 4, vector table entry IVTBASE + 0x08 (IVTBASE resets to 0x0008) |
| 6 | 0x0012 | CLC1 | __interrupt(irq(CLC1)) | CLC1 Interrupt; IRQ 5, vector table entry IVTBASE + 0x0A (IVTBASE resets to 0x0008) |
| 7 | 0x0014 | CRC | __interrupt(irq(CRC)) | CRC Interrupt; IRQ 6, vector table entry IVTBASE + 0x0C (IVTBASE resets to 0x0008) |
| 8 | 0x0016 | IOC | __interrupt(irq(IOC)) | Interrupt on change; IRQ 7, vector table entry IVTBASE + 0x0E (IVTBASE resets to 0x0008) |
| 9 | 0x0018 | INT0 | __interrupt(irq(INT0)) | External Interrupt 0; IRQ 8, vector table entry IVTBASE + 0x10 (IVTBASE resets to 0x0008) |
| 10 | 0x001A | ZCD | __interrupt(irq(ZCD)) | ZCD Interrupt; IRQ 9, vector table entry IVTBASE + 0x12 (IVTBASE resets to 0x0008) |
| 11 | 0x001C | AD | __interrupt(irq(AD)) | ADC Interrupt; IRQ 10, vector table entry IVTBASE + 0x14 (IVTBASE resets to 0x0008) |
| 12 | 0x001E | ACT | __interrupt(irq(ACT)) | Active Clock Tuning Interrupt; IRQ 11, vector table entry IVTBASE + 0x16 (IVTBASE resets to 0x0008) |
| 13 | 0x0020 | CMP1 | __interrupt(irq(CMP1)) | Comparator 1 Interrupt; IRQ 12, vector table entry IVTBASE + 0x18 (IVTBASE resets to 0x0008) |
| 14 | 0x0022 | SMT1 | __interrupt(irq(SMT1)) | SMT1 Interrupt; IRQ 13, vector table entry IVTBASE + 0x1A (IVTBASE resets to 0x0008) |
| 15 | 0x0024 | SMT1PRA | __interrupt(irq(SMT1PRA)) | SMT1 Period Acquisition Interrupt; IRQ 14, vector table entry IVTBASE + 0x1C (IVTBASE resets to 0x0008) |
| 16 | 0x0026 | SMT1PWA | __interrupt(irq(SMT1PWA)) | SMT1 Pulse width acqusition Interrupt; IRQ 15, vector table entry IVTBASE + 0x1E (IVTBASE resets to 0x0008) |
| 17 | 0x0028 | ADT | __interrupt(irq(ADT)) | ADC Threshold Interrupt; IRQ 16, vector table entry IVTBASE + 0x20 (IVTBASE resets to 0x0008) |
| 21 | 0x0030 | DMA1SCNT | __interrupt(irq(DMA1SCNT)) | DMA1 Source count Interrupt; IRQ 20, vector table entry IVTBASE + 0x28 (IVTBASE resets to 0x0008) |
| 22 | 0x0032 | DMA1DCNT | __interrupt(irq(DMA1DCNT)) | DMA1 Destination count Interrupt; IRQ 21, vector table entry IVTBASE + 0x2A (IVTBASE resets to 0x0008) |
| 23 | 0x0034 | DMA1OR | __interrupt(irq(DMA1OR)) | DMA1 Overflow Interrupt; IRQ 22, vector table entry IVTBASE + 0x2C (IVTBASE resets to 0x0008) |
| 24 | 0x0036 | DMA1A | __interrupt(irq(DMA1A)) | DMA1 Abort Interrupt; IRQ 23, vector table entry IVTBASE + 0x2E (IVTBASE resets to 0x0008) |
| 25 | 0x0038 | SPI1RX | __interrupt(irq(SPI1RX)) | SPI1 Receive Interrupt; IRQ 24, vector table entry IVTBASE + 0x30 (IVTBASE resets to 0x0008) |
| 26 | 0x003A | SPI1TX | __interrupt(irq(SPI1TX)) | SPI1 Transmit Interrupt; IRQ 25, vector table entry IVTBASE + 0x32 (IVTBASE resets to 0x0008) |
| 27 | 0x003C | SPI1 | __interrupt(irq(SPI1)) | SPI1 Interrupt; IRQ 26, vector table entry IVTBASE + 0x34 (IVTBASE resets to 0x0008) |
| 28 | 0x003E | TMR2 | __interrupt(irq(TMR2)) | Timer2 Interrupt; IRQ 27, vector table entry IVTBASE + 0x36 (IVTBASE resets to 0x0008) |
| 29 | 0x0040 | TMR1 | __interrupt(irq(TMR1)) | Timer1 Interrupt; IRQ 28, vector table entry IVTBASE + 0x38 (IVTBASE resets to 0x0008) |
| 30 | 0x0042 | TMR1G | __interrupt(irq(TMR1G)) | Timer1 Gate Interrupt; IRQ 29, vector table entry IVTBASE + 0x3A (IVTBASE resets to 0x0008) |
| 31 | 0x0044 | CCP1 | __interrupt(irq(CCP1)) | CCP1 Interrupt; IRQ 30, vector table entry IVTBASE + 0x3C (IVTBASE resets to 0x0008) |
| 32 | 0x0046 | TMR0 | __interrupt(irq(TMR0)) | Timer0 Interrupt; IRQ 31, vector table entry IVTBASE + 0x3E (IVTBASE resets to 0x0008) |
| 33 | 0x0048 | U1RX | __interrupt(irq(U1RX)) | UART1 Receive Interrupt; IRQ 32, vector table entry IVTBASE + 0x40 (IVTBASE resets to 0x0008) |
| 34 | 0x004A | U1TX | __interrupt(irq(U1TX)) | UART1 Transmit Interrupt; IRQ 33, vector table entry IVTBASE + 0x42 (IVTBASE resets to 0x0008) |
| 35 | 0x004C | U1E | __interrupt(irq(U1E)) | UART1 Error Interrupt; IRQ 34, vector table entry IVTBASE + 0x44 (IVTBASE resets to 0x0008) |
| 36 | 0x004E | U1 | __interrupt(irq(U1)) | UART1 Interrupt; IRQ 35, vector table entry IVTBASE + 0x46 (IVTBASE resets to 0x0008) |
| 37 | 0x0050 | TMR3 | __interrupt(irq(TMR3)) | Timer3 Interrupt; IRQ 36, vector table entry IVTBASE + 0x48 (IVTBASE resets to 0x0008) |
| 38 | 0x0052 | TMR3G | __interrupt(irq(TMR3G)) | Timer3 Gate Interrupt; IRQ 37, vector table entry IVTBASE + 0x4A (IVTBASE resets to 0x0008) |
| 39 | 0x0054 | PWM1PR | __interrupt(irq(PWM1PR)) | PWM1 Period Interrupt; IRQ 38, vector table entry IVTBASE + 0x4C (IVTBASE resets to 0x0008) |
| 40 | 0x0056 | PWM1 | __interrupt(irq(PWM1)) | PWM1 Interrupt; IRQ 39, vector table entry IVTBASE + 0x4E (IVTBASE resets to 0x0008) |
| 41 | 0x0058 | SPI2RX | __interrupt(irq(SPI2RX)) | SPI2 Receive Interrupt; IRQ 40, vector table entry IVTBASE + 0x50 (IVTBASE resets to 0x0008) |
| 42 | 0x005A | SPI2TX | __interrupt(irq(SPI2TX)) | SPI2 Transmit Interrupt; IRQ 41, vector table entry IVTBASE + 0x52 (IVTBASE resets to 0x0008) |
| 43 | 0x005C | SPI2 | __interrupt(irq(SPI2)) | SPI2 Interrupt; IRQ 42, vector table entry IVTBASE + 0x54 (IVTBASE resets to 0x0008) |
| 45 | 0x0060 | CMP2 | __interrupt(irq(CMP2)) | Comparator 2 Interrupt; IRQ 44, vector table entry IVTBASE + 0x58 (IVTBASE resets to 0x0008) |
| 46 | 0x0062 | CLC2 | __interrupt(irq(CLC2)) | CLC2 Interrupt; IRQ 45, vector table entry IVTBASE + 0x5A (IVTBASE resets to 0x0008) |
| 47 | 0x0064 | PWM2PR | __interrupt(irq(PWM2PR)) | PWM2 Period Interrupt; IRQ 46, vector table entry IVTBASE + 0x5C (IVTBASE resets to 0x0008) |
| 48 | 0x0066 | PWM2 | __interrupt(irq(PWM2)) | PWM2 Interrupt; IRQ 47, vector table entry IVTBASE + 0x5E (IVTBASE resets to 0x0008) |
| 49 | 0x0068 | INT1 | __interrupt(irq(INT1)) | External Interrupt 1; IRQ 48, vector table entry IVTBASE + 0x60 (IVTBASE resets to 0x0008) |
| 51 | 0x006C | CWG1 | __interrupt(irq(CWG1)) | CWG Interrupt; IRQ 50, vector table entry IVTBASE + 0x64 (IVTBASE resets to 0x0008) |
| 52 | 0x006E | NCO1 | __interrupt(irq(NCO1)) | NCO1 Interrupt; IRQ 51, vector table entry IVTBASE + 0x66 (IVTBASE resets to 0x0008) |
| 53 | 0x0070 | DMA2SCNT | __interrupt(irq(DMA2SCNT)) | DMA2 Source count Interrupt; IRQ 52, vector table entry IVTBASE + 0x68 (IVTBASE resets to 0x0008) |
| 54 | 0x0072 | DMA2DCNT | __interrupt(irq(DMA2DCNT)) | DMA2 Destination count Interrupt; IRQ 53, vector table entry IVTBASE + 0x6A (IVTBASE resets to 0x0008) |
| 55 | 0x0074 | DMA2OR | __interrupt(irq(DMA2OR)) | DMA2 Overflow Interrupt; IRQ 54, vector table entry IVTBASE + 0x6C (IVTBASE resets to 0x0008) |
| 56 | 0x0076 | DMA2A | __interrupt(irq(DMA2A)) | DMA2 Abort Interrupt; IRQ 55, vector table entry IVTBASE + 0x6E (IVTBASE resets to 0x0008) |
| 57 | 0x0078 | I2C1RX | __interrupt(irq(I2C1RX)) | I2C1 Receive Interrupt; IRQ 56, vector table entry IVTBASE + 0x70 (IVTBASE resets to 0x0008) |
| 58 | 0x007A | I2C1TX | __interrupt(irq(I2C1TX)) | I2C1 Transmit Interrupt; IRQ 57, vector table entry IVTBASE + 0x72 (IVTBASE resets to 0x0008) |
| 59 | 0x007C | I2C1 | __interrupt(irq(I2C1)) | I2C1 Interrupt; IRQ 58, vector table entry IVTBASE + 0x74 (IVTBASE resets to 0x0008) |
| 60 | 0x007E | I2C1E | __interrupt(irq(I2C1E)) | I2C1 Error Interrupt; IRQ 59, vector table entry IVTBASE + 0x76 (IVTBASE resets to 0x0008) |
| 62 | 0x0082 | CLC3 | __interrupt(irq(CLC3)) | CLC3 Interrupt; IRQ 61, vector table entry IVTBASE + 0x7A (IVTBASE resets to 0x0008) |
| 63 | 0x0084 | PWM3PR | __interrupt(irq(PWM3PR)) | PWM3 Period Interrupt; IRQ 62, vector table entry IVTBASE + 0x7C (IVTBASE resets to 0x0008) |
| 64 | 0x0086 | PWM3 | __interrupt(irq(PWM3)) | PWM3 Interrupt; IRQ 63, vector table entry IVTBASE + 0x7E (IVTBASE resets to 0x0008) |
| 65 | 0x0088 | U2RX | __interrupt(irq(U2RX)) | UART2 Receive Interrupt; IRQ 64, vector table entry IVTBASE + 0x80 (IVTBASE resets to 0x0008) |
| 66 | 0x008A | U2TX | __interrupt(irq(U2TX)) | UART2 Transmit Interrupt; IRQ 65, vector table entry IVTBASE + 0x82 (IVTBASE resets to 0x0008) |
| 67 | 0x008C | U2E | __interrupt(irq(U2E)) | UART2 Error Interrupt; IRQ 66, vector table entry IVTBASE + 0x84 (IVTBASE resets to 0x0008) |
| 68 | 0x008E | U2 | __interrupt(irq(U2)) | UART2 Interrupt; IRQ 67, vector table entry IVTBASE + 0x86 (IVTBASE resets to 0x0008) |
| 70 | 0x0092 | CLC4 | __interrupt(irq(CLC4)) | CLC4 Interrupt; IRQ 69, vector table entry IVTBASE + 0x8A (IVTBASE resets to 0x0008) |
| 72 | 0x0096 | SCAN | __interrupt(irq(SCAN)) | Scanner Interrupt; IRQ 71, vector table entry IVTBASE + 0x8E (IVTBASE resets to 0x0008) |
| 73 | 0x0098 | U3RX | __interrupt(irq(U3RX)) | UART3 Receive Interrupt; IRQ 72, vector table entry IVTBASE + 0x90 (IVTBASE resets to 0x0008) |
| 74 | 0x009A | U3TX | __interrupt(irq(U3TX)) | UART3 Transmit Interrupt; IRQ 73, vector table entry IVTBASE + 0x92 (IVTBASE resets to 0x0008) |
| 75 | 0x009C | U3E | __interrupt(irq(U3E)) | UART3 Error Interrupt; IRQ 74, vector table entry IVTBASE + 0x94 (IVTBASE resets to 0x0008) |
| 76 | 0x009E | U3 | __interrupt(irq(U3)) | UART3 Interrupt; IRQ 75, vector table entry IVTBASE + 0x96 (IVTBASE resets to 0x0008) |
| 77 | 0x00A0 | DMA3SCNT | __interrupt(irq(DMA3SCNT)) | DMA3 Source count Interrupt; IRQ 76, vector table entry IVTBASE + 0x98 (IVTBASE resets to 0x0008) |
| 78 | 0x00A2 | DMA3DCNT | __interrupt(irq(DMA3DCNT)) | DMA3 Destination count Interrupt; IRQ 77, vector table entry IVTBASE + 0x9A (IVTBASE resets to 0x0008) |
| 79 | 0x00A4 | DMA3OR | __interrupt(irq(DMA3OR)) | DMA3 Overflow Interrupt; IRQ 78, vector table entry IVTBASE + 0x9C (IVTBASE resets to 0x0008) |
| 80 | 0x00A6 | DMA3A | __interrupt(irq(DMA3A)) | DMA3 Abort Interrupt; IRQ 79, vector table entry IVTBASE + 0x9E (IVTBASE resets to 0x0008) |
| 81 | 0x00A8 | INT2 | __interrupt(irq(INT2)) | External Interrupt 2; IRQ 80, vector table entry IVTBASE + 0xA0 (IVTBASE resets to 0x0008) |
| 84 | 0x00AE | TMR4 | __interrupt(irq(TMR4)) | Timer4 Interrupt; IRQ 83, vector table entry IVTBASE + 0xA6 (IVTBASE resets to 0x0008) |
| 85 | 0x00B0 | DMA4SCNT | __interrupt(irq(DMA4SCNT)) | DMA4 Source count Interrupt; IRQ 84, vector table entry IVTBASE + 0xA8 (IVTBASE resets to 0x0008) |
| 86 | 0x00B2 | DMA4DCNT | __interrupt(irq(DMA4DCNT)) | DMA4 Destination count Interrupt; IRQ 85, vector table entry IVTBASE + 0xAA (IVTBASE resets to 0x0008) |
| 87 | 0x00B4 | DMA4OR | __interrupt(irq(DMA4OR)) | DMA4 Overflow Interrupt; IRQ 86, vector table entry IVTBASE + 0xAC (IVTBASE resets to 0x0008) |
| 88 | 0x00B6 | DMA4A | __interrupt(irq(DMA4A)) | DMA4 Abort Interrupt; IRQ 87, vector table entry IVTBASE + 0xAE (IVTBASE resets to 0x0008) |