PIC18F1220 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0xCF default 0xCF IESO Internal External Switchover bit Internal External Switchover mode disabled Internal External Switchover mode enabled FSCM Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled OSC Oscillator Selection bits LP Oscillator XT Oscillator HS Oscillator EC oscillator, CLKO function on RA6 EC oscillator, port function on RA6 HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) External RC oscillator, port function on RA6 Internal RC oscillator, port function on RA6 and port function on RA7 Internal RC oscillator, CLKO function on RA6 and port function on RA7 External RC oscillator, CLKO function on RA6 15 (not named) CONFIG2L · 0x300002 0x0F default 0x0F BORV Brown-out Reset Voltage bits VBOR set to 4.5V VBOR set to 4.2V VBOR set to 2.7V 3 (not named) BOR Brown-out Reset Enable bit Brown-out Reset disabled Brown-out Reset enabled PWRT Power-up Timer Enable bit PWRT enabled PWRT disabled CONFIG2H · 0x300003 0x1F default 0x1F WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 WDT Watchdog Timer Enable bit WDT disabled (control is placed on the SWDTEN bit) WDT enabled CONFIG3H · 0x300005 0x80 default 0x80 MCLRE MCLR Pin Enable bit RA5 input pin enabled, MCLR disabled MCLR pin enabled, RA5 input pin disabled CONFIG4L · 0x300006 0x85 default 0x85 DEBUG Background Debugger Enable bit Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins LVP Low-Voltage ICSP Enable bit Low-Voltage ICSP disabled Low-Voltage ICSP enabled STVR Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset CONFIG5L · 0x300008 0x03 default 0x03 CP1 Code Protection bit Block 1 (000800-000FFFh) code-protected Block 1 (000800-000FFFh) not code-protected CP0 Code Protection bit Block 0 (00200-0007FFh) code-protected Block 0 (00200-0007FFh) not code-protected CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EEPROM Code Protection bit Data EEPROM code-protected Data EEPROM not code-protected CPB Boot Block Code Protection bit Boot Block (000000-0001FFh) code-protected Boot Block (000000-0001FFh) not code-protected CONFIG6L · 0x30000A 0x03 default 0x03 WRT1 Write Protection bit Block 1 (000800-000FFFh) write-protected Block 1 (000800-000FFFh) not write-protected WRT0 Write Protection bit Block 0 (00200-000F7Fh) write-protected Block 0 (00200-0007FFh) not write-protected CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EEPROM Write Protection bit Data EEPROM write-protected Data EEPROM not write-protected WRTB Boot Block Write Protection bit Boot Block (000000-0001FFh) write-protected Boot Block (000000-0001FFh) not write-protected WRTC Configuration Register Write Protection bit Configuration registers (300000-3000FFh) write-protected Configuration registers (300000-3000FFh) not write-protected CONFIG7L · 0x30000C 0x03 default 0x03 EBTR1 Table Read Protection bit Block 1 (000800-000FFFh) protected from table reads executed in other blocks Block 1 (000800-000FFFh) not protected from table reads executed in other blocks EBTR0 Table Read Protection bit Block 0 (00200-0007FFh) protected from table reads executed in other blocks Block 0 (00200-0007FFh) not protected from table reads executed in other blocks CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Boot Block Table Read Protection bit Boot Block (000000-0001FFh) protected from table reads executed in other blocks Boot Block (000000-0001FFh) not protected from table reads executed in other blocks 
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