PIC18F14K22LIN configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0x27 default 0x27 IESO Internal/External Oscillator Switchover bit Oscillator Switchover mode disabled Oscillator Switchover mode enabled FCMEN Fail-Safe Clock Monitor Enable Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled PCLKEN Primary Clock Enable bit Primary clock is under software control Primary clock enabled PLLEN 4 X PLL Enable bit PLL is under software control Oscillator multiplied by 4 FOSC Oscillator Selection bits LP oscillator XT oscillator HS oscillator External RC oscillator, CLKOUT function on OSC2 EC, CLKOUT function on OSC2 (high) EC (high) External RC oscillator Internal RC oscillator Internal RC oscillator, CLKOUT function on OSC2 EC, CLKOUT function on OSC2 (medium) EC (medium) EC, CLKOUT function on OSC2 (low) EC (low) CONFIG2L · 0x300002 0x1F default 0x1F BORV Brown Out Reset Voltage bits VBOR set to 3.0 V nominal VBOR set to 2.7 V nominal VBOR set to 2.2 V nominal VBOR set to 1.9 V nominal BOREN Brown-out Reset Enable bits Brown-out Reset disabled in hardware and software Brown-out Reset enabled and controlled by software (SBOREN is enabled) Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) Brown-out Reset enabled in hardware only (SBOREN is disabled) PWRTEN Power-up Timer Enable bit PWRT enabled PWRT disabled CONFIG2H · 0x300003 0x1F default 0x1F WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 WDTEN Watchdog Timer Enable bit WDT is controlled by SWDTEN bit of the WDTCON register WDT is always enabled. SWDTEN bit has no effect. CONFIG3H · 0x300005 0x88 default 0x88 MCLRE MCLR Pin Enable bit RA3 input pin enabled; MCLR disabled MCLR pin enabled, RA3 input pin disabled HFOFST HFINTOSC Fast Start-up bit The system clock is held off until the HFINTOSC is stable. HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. CONFIG4L · 0x300006 0x85 default 0x85 DEBUG Background Debugger Enable bit Background debugger enabled, RA0 and RA1 are dedicated to In-Circuit Debug Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins XINST Extended Instruction Set Enable bit Instruction set extension and Indexed Addressing mode disabled (Legacy mode) Instruction set extension and Indexed Addressing mode enabled BBSIZ Boot Block Size Select bit 1kW boot block size 2kW boot block size LVP Single-Supply ICSP Enable bit Single-Supply ICSP disabled Single-Supply ICSP enabled STVREN Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset CONFIG5L · 0x300008 0x03 default 0x03 CP1 Code Protection bit Block 1 code-protected Block 1 not code-protected CP0 Code Protection bit Block 0 code-protected Block 0 not code-protected CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EEPROM Code Protection bit Data EEPROM code-protected Data EEPROM not code-protected CPB Boot Block Code Protection bit Boot block code-protected Boot block not code-protected CONFIG6L · 0x30000A 0x03 default 0x03 WRT1 Write Protection bit Block 1 write-protected Block 1 not write-protected WRT0 Write Protection bit Block 0 write-protected Block 0 not write-protected CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EEPROM Write Protection bit Data EEPROM write-protected Data EEPROM not write-protected WRTB Boot Block Write Protection bit Boot block write-protected Boot block not write-protected WRTC Configuration Register Write Protection bit Configuration registers write-protected Configuration registers not write-protected CONFIG7L · 0x30000C 0x03 default 0x03 EBTR1 Table Read Protection bit Block 1 protected from table reads executed in other blocks Block 1 not protected from table reads executed in other blocks EBTR0 Table Read Protection bit Block 0 protected from table reads executed in other blocks Block 0 not protected from table reads executed in other blocks CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Boot Block Table Read Protection bit Boot block protected from table reads executed in other blocks Boot block not protected from table reads executed in other blocks 
BETA