PIC18F14Q40 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1 · 0x300000 0xFF default 0xFF RSTOSC Reset Oscillator Selection HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1 Reserved EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits Reserved Secondary Oscillator Low-Frequency Oscillator HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1 EXTOSC operating per FEXTOSC bits (device manufacturing default) FEXTOSC External Oscillator Selection LP (crystal oscillator) optimized for 32.768 kHz XT (crystal oscillator) above 100 kHz, below 8 MHz HS (crystal oscillator) above 8 MHz Reserved (DO NOT USE) Oscillator not enabled EC (external clock) below 100 kHz EC (external clock) for 500 kHz to 8 MHz EC (external clock) above 8 MHz CONFIG2 · 0x300001 0xFF default 0xFF FCMENS Fail-Safe Clock Monitor - Secondary XTAL Enable bit Fail-Safe Clock Monitor Disabled Fail-Safe Clock Monitor enabled; timer will flag FSCMP bit and OSFIF interrupt on SOSC failure. FCMENP Fail-Safe Clock Monitor - Primary XTAL Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled; timer will flag FSCMP bit and OSFIF interrupt on EXTOSC failure. FCMEN Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled CSWEN Clock Switch Enable bit The NOSC and NDIV bits cannot be changed by user software Writing to NOSC and NDIV is allowed PR1WAY PRLOCKED One-Way Set Enable bit PRLOCKED bit can be set and cleared repeatedly PRLOCKED bit can be cleared and set only once CLKOUTEN Clock out Enable bit CLKOUT function is enabled CLKOUT function is disabled CONFIG3 · 0x300002 0xFF default 0xFF BOREN Brown-out Reset Enable bits Brown-out Reset disabled Brown-out Reset enabled according to SBOREN Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored Brown-out Reset enabled , SBOREN bit is ignored LPBOREN Low Power BOR Enable bit Low-Power BOR enabled Low-Power BOR disabled IVT1WAY IVTLOCK bit One-way set enable bit IVTLOCKED bit can be cleared and set repeatedly IVTLOCKED bit can be cleared and set only once MVECEN Multi-vector enable bit Interrupt contoller does not use vector table to prioritze interrupts Multi-vector enabled, Vector table used for interrupts PWRTS Power-up timer selection bits PWRT set at 1ms PWRT set at 16ms PWRT set at 64ms PWRT is disabled MCLRE MCLR Enable bit If LVP = 0, MCLR pin function is port defined function; If LVP =1, RE3 pin fuction is MCLR If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR CONFIG4 · 0x300003 0xFF default 0xFF XINST Extended Instruction Set Enable bit Extended Instruction Set and Indexed Addressing Mode enabled Extended Instruction Set and Indexed Addressing Mode disabled LVP Low Voltage Programming Enable bit HV on MCLR/VPP must be used for programming Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored STVREN Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset PPS1WAY PPSLOCK bit One-Way Set Enable bit PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence) PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle ZCD ZCD Disable bit ZCD module is always enabled; ZCDMD and ZCDSEN bits are ignored ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON BORV Brown-out Reset Voltage Selection bits Brown-out Reset Voltage (VBOR) set to 2.8V Brown-out Reset Voltage (VBOR) set to 2.7V Brown-out Reset Voltage (VBOR) set to 2.45V Brown-out Reset Voltage (VBOR) set to 1.9V CONFIG5 · 0x300004 0xFF default 0xFF WDTE WDT operating mode WDT Disabled; SWDTEN is ignored WDT enabled/disabled by SWDTEN bit WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored WDT enabled regardless of sleep; SWDTEN is ignored WDTCPS WDT Period selection bits Divider ratio 1:32 Divider ratio 1:64 Divider ratio 1:128 Divider ratio 1:256 Divider ratio 1:512 Divider ratio 1:1024 Divider ratio 1:2048 Divider ratio 1:4096 Divider ratio 1:8192 Divider ratio 1:16384 Divider ratio 1:32768 Divider ratio 1:65536 Divider ratio 1:131072 Divider ratio 1:262144 Divider ratio 1:524299 Divider ratio 1:1048576 Divider ratio 1:2097152 Divider ratio 1:4194304 Divider ratio 1:8388608 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:65536; software control of WDTPS CONFIG6 · 0x300005 0xFF default 0xFF WDTCCS WDT input clock selector WDT reference clock is the 31.0 kHz LFINTOSC WDT reference clock is the 31.25kHz MFINTOSC output WDT reference clock is SOSC Software Control WDTCWS WDT Window Select bits window delay = 87.5; no software control; keyed access required window delay = 75 percent of time; no software control; keyed access required window delay = 62.5 percent of time; no software control; keyed access required window delay = 50 percent of time; no software control; keyed access required window delay = 37.5 percent of time; no software control; keyed access required window delay = 25 percent of time; no software control; keyed access required window always open (100%); no software control; keyed access required window always open (100%); software control; keyed access not required CONFIG7 · 0x300006 0xFF default 0xFF DEBUG Background Debugger Background Debugger enabled Background Debugger disabled SAFEN Storage Area Flash enable bit SAF enabled SAF disabled BBEN Boot Block enable bit Boot block enabled Boot block disabled BBSIZE Boot Block Size selection bits Boot Block size is 4096 words Boot Block size is 2048 words Boot Block size is 1024 words Boot Block size is 512 words CONFIG8 · 0x300007 0xFF default 0xFF WRTAPP Application Block write protection bit Application Block write protected Application Block not write protected WRTSAF SAF Write protection bit SAF Write Protected SAF not Write Protected WRTD Data EEPROM Write Protection bit Data EEPROM Write protected Data EEPROM not Write protected WRTC Configuration Register Write Protection bit Configuration registers Write protected Configuration registers not Write protected WRTB Boot Block Write Protection bit Boot Block Write protected Boot Block not Write protected CONFIG9 · 0x300008 0xFF default 0xFF CP PFM and Data EEPROM Code Protection bit PFM and Data EEPROM code protection enabled PFM and Data EEPROM code protection disabled 
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