PIC18F2685 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0x07 default 0x07 IESO Internal/External Oscillator Switchover bit Oscillator Switchover mode disabled Oscillator Switchover mode enabled FCMEN Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled OSC Oscillator Selection bits LP oscillator XT oscillator HS oscillator External RC oscillator, CLKO function on RA6 EC oscillator, CLKO function on RA6 EC oscillator, port function on RA6 HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) External RC oscillator, port function on RA6 Internal oscillator block, port function on RA6 and RA7 Internal oscillator block, CLKO function on RA6, port function on RA7 CONFIG2L · 0x300002 0x1F default 0x1F BORV Brown-out Reset Voltage bits VBOR set to 4.6V VBOR set to 4.3V VBOR set to 2.8V VBOR set to 2.1V BOREN Brown-out Reset Enable bits Brown-out Reset disabled in hardware and software Brown-out Reset enabled and controlled by software (SBOREN is enabled) Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) Brown-out Reset enabled in hardware only (SBOREN is disabled) PWRT Power-up Timer Enable bit PWRT enabled PWRT disabled CONFIG2H · 0x300003 0x1F default 0x1F WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 WDT Watchdog Timer Enable bit WDT disabled (control is placed on the SWDTEN bit) WDT enabled CONFIG3H · 0x300005 0x82 default 0x82 MCLRE MCLR Pin Enable bit RE3 input pin enabled; MCLR disabled MCLR pin enabled; RE3 input pin disabled LPT1OSC Low-Power Timer 1 Oscillator Enable bit Timer1 configured for higher power operation Timer1 configured for low-power operation PBADEN PORTB A/D Enable bit PORTB<4:0> pins are configured as digital I/O on Reset PORTB<4:0> pins are configured as analog input channels on Reset CONFIG4L · 0x300006 0x85 default 0x85 DEBUG Background Debugger Enable bit Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins XINST Extended Instruction Set Enable bit Instruction set extension and Indexed Addressing mode disabled (Legacy mode) Instruction set extension and Indexed Addressing mode enabled BBSIZ Boot Block Size Select bits 1K words (2K bytes) Boot Block 2K words (4K bytes) Boot Block 4K words (8K bytes) Boot Block LVP Single-Supply ICSP Enable bit Single-Supply ICSP disabled Single-Supply ICSP enabled STVREN Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset CONFIG5L · 0x300008 0x3F default 0x3F CP5 Code Protection bit Block 5 (014000-017FFFh) code-protected Block 5 (014000-017FFFh) not code-protected CP4 Code Protection bit Block 4 (010000-013FFFh) code-protected Block 4 (010000-013FFFh) not code-protected CP3 Code Protection bit Block 3 (00C000-00FFFFh) code-protected Block 3 (00C000-00FFFFh) not code-protected CP2 Code Protection bit Block 2 (008000-00BFFFh) code-protected Block 2 (008000-00BFFFh) not code-protected CP1 Code Protection bit Block 1 (004000-007FFFh) code-protected Block 1 (004000-007FFFh) not code-protected CP0 Code Protection bit Block 0 (000800-003FFFh) code-protected Block 0 (000800-003FFFh) not code-protected CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EEPROM Code Protection bit Data EEPROM code-protected Data EEPROM not code-protected CPB Boot Block Code Protection bit Boot block (000000-0007FFh) code-protected Boot block (000000-0007FFh) not code-protected CONFIG6L · 0x30000A 0x3F default 0x3F WRT5 Write Protection bit Block 5 (014000-017FFFh) write-protected Block 5 (014000-017FFFh) not write-protected WRT4 Write Protection bit Block 4 (010000-013FFFh) write-protected Block 4 (010000-013FFFh) not write-protected WRT3 Write Protection bit Block 3 (00C000-00FFFFh) write-protected Block 3 (00C000-00FFFFh) not write-protected WRT2 Write Protection bit Block 2 (008000-00BFFFh) write-protected Block 2 (008000-00BFFFh) not write-protected WRT1 Write Protection bit Block 1 (004000-007FFFh) write-protected Block 1 (004000-007FFFh) not write-protected WRT0 Write Protection bit Block 0 (000800-003FFFh) write-protected Block 0 (000800-003FFFh) not write-protected CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EEPROM Write Protection bit Data EEPROM write-protected Data EEPROM not write-protected WRTB Boot Block Write Protection bit Boot block (000000-0007FFh) write-protected Boot block (000000-0007FFh) not write-protected WRTC Configuration Register Write Protection bit Configuration registers (300000-3000FFh) write-protected Configuration registers (300000-3000FFh) not write-protected CONFIG7L · 0x30000C 0x3F default 0x3F EBTR5 Table Read Protection bit Block 5 (014000-017FFFh) protected from table reads executed in other blocks Block 5 (014000-017FFFh) not protected from table reads executed in other blocks EBTR4 Table Read Protection bit Block 4 (010000-013FFFh) protected from table reads executed in other blocks Block 4 (010000-013FFFh) not protected from table reads executed in other blocks EBTR3 Table Read Protection bit Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks EBTR2 Table Read Protection bit Block 2 (008000-00BFFFh) protected from table reads executed in other blocks Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks EBTR1 Table Read Protection bit Block 1 (004000-007FFFh) protected from table reads executed in other blocks Block 1 (004000-007FFFh) not protected from table reads executed in other blocks EBTR0 Table Read Protection bit Block 0 (000800-003FFFh) protected from table reads executed in other blocks Block 0 (000800-003FFFh) not protected from table reads executed in other blocks CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Boot Block Table Read Protection bit Boot block (000000-0007FFh) protected from table reads executed in other blocks Boot block (000000-0007FFh) not protected from table reads executed in other blocks 
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