BETAPIC18F27Q84 interrupt vectors
Reset at 0x0000, then a vector table of 125 sources: each source's entry is at IVTBASE + 2 × its IRQ number (IVTBASE is 0x0008 after reset) and holds its handler's address. With MVECEN off the chip uses 0x0008 and 0x0018 as the other PIC18s do. Each source has an enable bit and a flag (the Registers page lists them). In XC8 a handler is void __interrupt(irq(TMR0)) isr(void).
| Vector | Program address | Name | Handler | Source |
|---|---|---|---|---|
| 0 | 0x0000 | RESET | reset: main() after start-up | Reset vector, address 0x0000 |
| 1 | 0x0008 | SWINT | __interrupt(irq(SWINT)) | Software Interrupt; IRQ 0, vector table entry IVTBASE + 0x00 (IVTBASE resets to 0x0008) |
| 2 | 0x000A | HLVD | __interrupt(irq(HLVD)) | HLVD Interrupt; IRQ 1, vector table entry IVTBASE + 0x02 (IVTBASE resets to 0x0008) |
| 3 | 0x000C | OSF | __interrupt(irq(OSF)) | Oscillator Failure Interrupt; IRQ 2, vector table entry IVTBASE + 0x04 (IVTBASE resets to 0x0008) |
| 4 | 0x000E | CSW | __interrupt(irq(CSW)) | Clock Switch Interrupt; IRQ 3, vector table entry IVTBASE + 0x06 (IVTBASE resets to 0x0008) |
| 5 | 0x0010 | TU16A | __interrupt(irq(TU16A)) | Universal Timer 16A Interrupt; IRQ 4, vector table entry IVTBASE + 0x08 (IVTBASE resets to 0x0008) |
| 6 | 0x0012 | CLC1 | __interrupt(irq(CLC1)) | CLC1 Interrupt; IRQ 5, vector table entry IVTBASE + 0x0A (IVTBASE resets to 0x0008) |
| 7 | 0x0014 | CAN | __interrupt(irq(CAN)) | CAN FD Interrupt; IRQ 6, vector table entry IVTBASE + 0x0C (IVTBASE resets to 0x0008) |
| 8 | 0x0016 | IOC | __interrupt(irq(IOC)) | Interrupt on change; IRQ 7, vector table entry IVTBASE + 0x0E (IVTBASE resets to 0x0008) |
| 9 | 0x0018 | INT0 | __interrupt(irq(INT0)) | External Interrupt 0; IRQ 8, vector table entry IVTBASE + 0x10 (IVTBASE resets to 0x0008) |
| 10 | 0x001A | ZCD | __interrupt(irq(ZCD)) | ZCD Interrupt; IRQ 9, vector table entry IVTBASE + 0x12 (IVTBASE resets to 0x0008) |
| 11 | 0x001C | AD | __interrupt(irq(AD)) | ADC Interrupt; IRQ 10, vector table entry IVTBASE + 0x14 (IVTBASE resets to 0x0008) |
| 12 | 0x001E | ACT | __interrupt(irq(ACT)) | ADC Treshold Interrupt; IRQ 11, vector table entry IVTBASE + 0x16 (IVTBASE resets to 0x0008) |
| 13 | 0x0020 | CM1 | __interrupt(irq(CM1)) | Comparator 1 Interrupt; IRQ 12, vector table entry IVTBASE + 0x18 (IVTBASE resets to 0x0008) |
| 14 | 0x0022 | SMT1 | __interrupt(irq(SMT1)) | SMT1 Interrupt; IRQ 13, vector table entry IVTBASE + 0x1A (IVTBASE resets to 0x0008) |
| 15 | 0x0024 | SMT1PRA | __interrupt(irq(SMT1PRA)) | ; IRQ 14, vector table entry IVTBASE + 0x1C (IVTBASE resets to 0x0008) |
| 16 | 0x0026 | SMT1PWA | __interrupt(irq(SMT1PWA)) | ; IRQ 15, vector table entry IVTBASE + 0x1E (IVTBASE resets to 0x0008) |
| 17 | 0x0028 | ADCH1 | __interrupt(irq(ADCH1)) | ADC Threshold Interrupt-Context 0; IRQ 16, vector table entry IVTBASE + 0x20 (IVTBASE resets to 0x0008) |
| 18 | 0x002A | ADCH2 | __interrupt(irq(ADCH2)) | ADC Threshold Interrupt-Context 1; IRQ 17, vector table entry IVTBASE + 0x22 (IVTBASE resets to 0x0008) |
| 19 | 0x002C | ADCH3 | __interrupt(irq(ADCH3)) | ADC Threshold Interrupt-Context 2; IRQ 18, vector table entry IVTBASE + 0x24 (IVTBASE resets to 0x0008) |
| 20 | 0x002E | ADCH4 | __interrupt(irq(ADCH4)) | ADC Threshold Interrupt-Context 3; IRQ 19, vector table entry IVTBASE + 0x26 (IVTBASE resets to 0x0008) |
| 21 | 0x0030 | DMA1SCNT | __interrupt(irq(DMA1SCNT)) | DMA1 Source count Interrupt; IRQ 20, vector table entry IVTBASE + 0x28 (IVTBASE resets to 0x0008) |
| 22 | 0x0032 | DMA1DCNT | __interrupt(irq(DMA1DCNT)) | DMA1 Destination count Interrupt; IRQ 21, vector table entry IVTBASE + 0x2A (IVTBASE resets to 0x0008) |
| 23 | 0x0034 | DMA1OR | __interrupt(irq(DMA1OR)) | DMA1 Overflow Interrupt; IRQ 22, vector table entry IVTBASE + 0x2C (IVTBASE resets to 0x0008) |
| 24 | 0x0036 | DMA1A | __interrupt(irq(DMA1A)) | DMA1 Abort Interrupt; IRQ 23, vector table entry IVTBASE + 0x2E (IVTBASE resets to 0x0008) |
| 25 | 0x0038 | SPI1RX | __interrupt(irq(SPI1RX)) | SPI1 Receive Interrupt; IRQ 24, vector table entry IVTBASE + 0x30 (IVTBASE resets to 0x0008) |
| 26 | 0x003A | SPI1TX | __interrupt(irq(SPI1TX)) | SPI1 Transmit Interrupt; IRQ 25, vector table entry IVTBASE + 0x32 (IVTBASE resets to 0x0008) |
| 27 | 0x003C | SPI1 | __interrupt(irq(SPI1)) | SPI1 Interrupt; IRQ 26, vector table entry IVTBASE + 0x34 (IVTBASE resets to 0x0008) |
| 28 | 0x003E | TMR2 | __interrupt(irq(TMR2)) | Timer 2 Interrupt; IRQ 27, vector table entry IVTBASE + 0x36 (IVTBASE resets to 0x0008) |
| 29 | 0x0040 | TMR1 | __interrupt(irq(TMR1)) | Timer 1 Interrupt; IRQ 28, vector table entry IVTBASE + 0x38 (IVTBASE resets to 0x0008) |
| 30 | 0x0042 | TMR1G | __interrupt(irq(TMR1G)) | Timer 1 Gate Interrupt; IRQ 29, vector table entry IVTBASE + 0x3A (IVTBASE resets to 0x0008) |
| 31 | 0x0044 | CCP1 | __interrupt(irq(CCP1)) | CCP1 Interrupt; IRQ 30, vector table entry IVTBASE + 0x3C (IVTBASE resets to 0x0008) |
| 32 | 0x0046 | TMR0 | __interrupt(irq(TMR0)) | Timer0 Interrupt; IRQ 31, vector table entry IVTBASE + 0x3E (IVTBASE resets to 0x0008) |
| 33 | 0x0048 | U1RX | __interrupt(irq(U1RX)) | UART1 Receive Interrupt; IRQ 32, vector table entry IVTBASE + 0x40 (IVTBASE resets to 0x0008) |
| 34 | 0x004A | U1TX | __interrupt(irq(U1TX)) | UART1 Transmit Interrupt; IRQ 33, vector table entry IVTBASE + 0x42 (IVTBASE resets to 0x0008) |
| 35 | 0x004C | U1E | __interrupt(irq(U1E)) | UART1 Error Interrupt; IRQ 34, vector table entry IVTBASE + 0x44 (IVTBASE resets to 0x0008) |
| 36 | 0x004E | U1 | __interrupt(irq(U1)) | UART1 Interrupt; IRQ 35, vector table entry IVTBASE + 0x46 (IVTBASE resets to 0x0008) |
| 37 | 0x0050 | CANRX | __interrupt(irq(CANRX)) | CAN FD Receive Interrupt; IRQ 36, vector table entry IVTBASE + 0x48 (IVTBASE resets to 0x0008) |
| 38 | 0x0052 | CANTX | __interrupt(irq(CANTX)) | CAN FD Transmit Interrupt; IRQ 37, vector table entry IVTBASE + 0x4A (IVTBASE resets to 0x0008) |
| 39 | 0x0054 | PWM1PR | __interrupt(irq(PWM1PR)) | PWM1 Period Interrupt; IRQ 38, vector table entry IVTBASE + 0x4C (IVTBASE resets to 0x0008) |
| 40 | 0x0056 | PWM1 | __interrupt(irq(PWM1)) | PWM1 Interrupt; IRQ 39, vector table entry IVTBASE + 0x4E (IVTBASE resets to 0x0008) |
| 41 | 0x0058 | SPI2RX | __interrupt(irq(SPI2RX)) | SPI2 Receive Interrupt; IRQ 40, vector table entry IVTBASE + 0x50 (IVTBASE resets to 0x0008) |
| 42 | 0x005A | SPI2TX | __interrupt(irq(SPI2TX)) | SPI2 Transmit Interrupt; IRQ 41, vector table entry IVTBASE + 0x52 (IVTBASE resets to 0x0008) |
| 43 | 0x005C | SPI2 | __interrupt(irq(SPI2)) | SPI 2 Interrupt; IRQ 42, vector table entry IVTBASE + 0x54 (IVTBASE resets to 0x0008) |
| 44 | 0x005E | TU16B | __interrupt(irq(TU16B)) | Universal Time 16B Interrupt; IRQ 43, vector table entry IVTBASE + 0x56 (IVTBASE resets to 0x0008) |
| 45 | 0x0060 | TMR3 | __interrupt(irq(TMR3)) | Timer 3 Interrupt; IRQ 44, vector table entry IVTBASE + 0x58 (IVTBASE resets to 0x0008) |
| 46 | 0x0062 | TMR3G | __interrupt(irq(TMR3G)) | Timer 3 Gate Interrupt; IRQ 45, vector table entry IVTBASE + 0x5A (IVTBASE resets to 0x0008) |
| 47 | 0x0064 | PWM2PR | __interrupt(irq(PWM2PR)) | PWM2 Period Interrupt; IRQ 46, vector table entry IVTBASE + 0x5C (IVTBASE resets to 0x0008) |
| 48 | 0x0066 | PWM2 | __interrupt(irq(PWM2)) | PWM2 Interrupt; IRQ 47, vector table entry IVTBASE + 0x5E (IVTBASE resets to 0x0008) |
| 49 | 0x0068 | INT1 | __interrupt(irq(INT1)) | External Interrupt 1; IRQ 48, vector table entry IVTBASE + 0x60 (IVTBASE resets to 0x0008) |
| 50 | 0x006A | CLC2 | __interrupt(irq(CLC2)) | CLC2 Interrupt; IRQ 49, vector table entry IVTBASE + 0x62 (IVTBASE resets to 0x0008) |
| 51 | 0x006C | CWG1 | __interrupt(irq(CWG1)) | CWG 1 Interrupt; IRQ 50, vector table entry IVTBASE + 0x64 (IVTBASE resets to 0x0008) |
| 52 | 0x006E | NCO1 | __interrupt(irq(NCO1)) | NCO 1 Interrupt; IRQ 51, vector table entry IVTBASE + 0x66 (IVTBASE resets to 0x0008) |
| 53 | 0x0070 | DMA2SCNT | __interrupt(irq(DMA2SCNT)) | DMA2 Source Count Interrupt; IRQ 52, vector table entry IVTBASE + 0x68 (IVTBASE resets to 0x0008) |
| 54 | 0x0072 | DMA2DCNT | __interrupt(irq(DMA2DCNT)) | DMA2 Destination Count Interrupt; IRQ 53, vector table entry IVTBASE + 0x6A (IVTBASE resets to 0x0008) |
| 55 | 0x0074 | DMA2OR | __interrupt(irq(DMA2OR)) | DMA2 Overflow Interrupt; IRQ 54, vector table entry IVTBASE + 0x6C (IVTBASE resets to 0x0008) |
| 56 | 0x0076 | DMA2A | __interrupt(irq(DMA2A)) | DMA2 Abort Interrupt; IRQ 55, vector table entry IVTBASE + 0x6E (IVTBASE resets to 0x0008) |
| 57 | 0x0078 | I2C1RX | __interrupt(irq(I2C1RX)) | I2C1 Receive Interrupt; IRQ 56, vector table entry IVTBASE + 0x70 (IVTBASE resets to 0x0008) |
| 58 | 0x007A | I2C1TX | __interrupt(irq(I2C1TX)) | I2C1 Transmit Interrupt; IRQ 57, vector table entry IVTBASE + 0x72 (IVTBASE resets to 0x0008) |
| 59 | 0x007C | I2C1 | __interrupt(irq(I2C1)) | I2C1 General Interrupt; IRQ 58, vector table entry IVTBASE + 0x74 (IVTBASE resets to 0x0008) |
| 60 | 0x007E | I2C1E | __interrupt(irq(I2C1E)) | I2C1 Error Interrupt; IRQ 59, vector table entry IVTBASE + 0x76 (IVTBASE resets to 0x0008) |
| 62 | 0x0082 | CLC3 | __interrupt(irq(CLC3)) | CLC3 Interrupt; IRQ 61, vector table entry IVTBASE + 0x7A (IVTBASE resets to 0x0008) |
| 63 | 0x0084 | PWM3PR | __interrupt(irq(PWM3PR)) | PWM3 Period Interrupt; IRQ 62, vector table entry IVTBASE + 0x7C (IVTBASE resets to 0x0008) |
| 64 | 0x0086 | PWM3 | __interrupt(irq(PWM3)) | PWM3 Interrupt; IRQ 63, vector table entry IVTBASE + 0x7E (IVTBASE resets to 0x0008) |
| 65 | 0x0088 | U2RX | __interrupt(irq(U2RX)) | UART2 Receive Interrupt; IRQ 64, vector table entry IVTBASE + 0x80 (IVTBASE resets to 0x0008) |
| 66 | 0x008A | U2TX | __interrupt(irq(U2TX)) | UART2 Transmit Interrupt; IRQ 65, vector table entry IVTBASE + 0x82 (IVTBASE resets to 0x0008) |
| 67 | 0x008C | U2E | __interrupt(irq(U2E)) | UART2 Error Interrupt; IRQ 66, vector table entry IVTBASE + 0x84 (IVTBASE resets to 0x0008) |
| 68 | 0x008E | U2 | __interrupt(irq(U2)) | UART2 Interrupt; IRQ 67, vector table entry IVTBASE + 0x86 (IVTBASE resets to 0x0008) |
| 69 | 0x0090 | TMR5 | __interrupt(irq(TMR5)) | Timer5 Interrupt; IRQ 68, vector table entry IVTBASE + 0x88 (IVTBASE resets to 0x0008) |
| 70 | 0x0092 | TMR5G | __interrupt(irq(TMR5G)) | Timer5 Gate Interrupt; IRQ 69, vector table entry IVTBASE + 0x8A (IVTBASE resets to 0x0008) |
| 71 | 0x0094 | CCP2 | __interrupt(irq(CCP2)) | CCP2 Interrupt; IRQ 70, vector table entry IVTBASE + 0x8C (IVTBASE resets to 0x0008) |
| 72 | 0x0096 | SCAN | __interrupt(irq(SCAN)) | Scanner Interrupt; IRQ 71, vector table entry IVTBASE + 0x8E (IVTBASE resets to 0x0008) |
| 73 | 0x0098 | U3RX | __interrupt(irq(U3RX)) | UART3 Receive Interrupt; IRQ 72, vector table entry IVTBASE + 0x90 (IVTBASE resets to 0x0008) |
| 74 | 0x009A | U3TX | __interrupt(irq(U3TX)) | UART3 Transmit Interrupt; IRQ 73, vector table entry IVTBASE + 0x92 (IVTBASE resets to 0x0008) |
| 75 | 0x009C | U3E | __interrupt(irq(U3E)) | UART3 Error Interrupt; IRQ 74, vector table entry IVTBASE + 0x94 (IVTBASE resets to 0x0008) |
| 76 | 0x009E | U3 | __interrupt(irq(U3)) | UART3 Interrupt; IRQ 75, vector table entry IVTBASE + 0x96 (IVTBASE resets to 0x0008) |
| 78 | 0x00A2 | CLC4 | __interrupt(irq(CLC4)) | CLC4 Interrupt; IRQ 77, vector table entry IVTBASE + 0x9A (IVTBASE resets to 0x0008) |
| 79 | 0x00A4 | PWM4PR | __interrupt(irq(PWM4PR)) | PWM4 Period Interrupt; IRQ 78, vector table entry IVTBASE + 0x9C (IVTBASE resets to 0x0008) |
| 80 | 0x00A6 | PWM4 | __interrupt(irq(PWM4)) | PWM4 Interrupt; IRQ 79, vector table entry IVTBASE + 0x9E (IVTBASE resets to 0x0008) |
| 81 | 0x00A8 | INT2 | __interrupt(irq(INT2)) | External Interrupt 2; IRQ 80, vector table entry IVTBASE + 0xA0 (IVTBASE resets to 0x0008) |
| 82 | 0x00AA | CLC5 | __interrupt(irq(CLC5)) | CLC5 Interrupt; IRQ 81, vector table entry IVTBASE + 0xA2 (IVTBASE resets to 0x0008) |
| 83 | 0x00AC | CWG2 | __interrupt(irq(CWG2)) | CWG2 Interrupt; IRQ 82, vector table entry IVTBASE + 0xA4 (IVTBASE resets to 0x0008) |
| 84 | 0x00AE | NCO2 | __interrupt(irq(NCO2)) | NCO2 Interrupt; IRQ 83, vector table entry IVTBASE + 0xA6 (IVTBASE resets to 0x0008) |
| 85 | 0x00B0 | DMA3SCNT | __interrupt(irq(DMA3SCNT)) | DMA3 Source count Interrupt; IRQ 84, vector table entry IVTBASE + 0xA8 (IVTBASE resets to 0x0008) |
| 86 | 0x00B2 | DMA3DCNT | __interrupt(irq(DMA3DCNT)) | DMA3 Destination count Interrupt; IRQ 85, vector table entry IVTBASE + 0xAA (IVTBASE resets to 0x0008) |
| 87 | 0x00B4 | DMA3OR | __interrupt(irq(DMA3OR)) | DMA3 Overflow Interrupt; IRQ 86, vector table entry IVTBASE + 0xAC (IVTBASE resets to 0x0008) |
| 88 | 0x00B6 | DMA3A | __interrupt(irq(DMA3A)) | DMA3 Abort Interrupt; IRQ 87, vector table entry IVTBASE + 0xAE (IVTBASE resets to 0x0008) |
| 89 | 0x00B8 | CCP3 | __interrupt(irq(CCP3)) | CCP3 Interrupt; IRQ 88, vector table entry IVTBASE + 0xB0 (IVTBASE resets to 0x0008) |
| 90 | 0x00BA | CLC6 | __interrupt(irq(CLC6)) | CLC6 Interrupt; IRQ 89, vector table entry IVTBASE + 0xB2 (IVTBASE resets to 0x0008) |
| 91 | 0x00BC | CWG3 | __interrupt(irq(CWG3)) | CWG3 Interrupt; IRQ 90, vector table entry IVTBASE + 0xB4 (IVTBASE resets to 0x0008) |
| 92 | 0x00BE | TMR4 | __interrupt(irq(TMR4)) | TMR4 Interrupt; IRQ 91, vector table entry IVTBASE + 0xB6 (IVTBASE resets to 0x0008) |
| 93 | 0x00C0 | DMA4SCNT | __interrupt(irq(DMA4SCNT)) | DMA4 Source count Interrupt; IRQ 92, vector table entry IVTBASE + 0xB8 (IVTBASE resets to 0x0008) |
| 94 | 0x00C2 | DMA4DCNT | __interrupt(irq(DMA4DCNT)) | DMA4 Destination count Interrupt; IRQ 93, vector table entry IVTBASE + 0xBA (IVTBASE resets to 0x0008) |
| 95 | 0x00C4 | DMA4OR | __interrupt(irq(DMA4OR)) | DMA4 Overflow Interrupt; IRQ 94, vector table entry IVTBASE + 0xBC (IVTBASE resets to 0x0008) |
| 96 | 0x00C6 | DMA4A | __interrupt(irq(DMA4A)) | DMA4 Abort Interrupt; IRQ 95, vector table entry IVTBASE + 0xBE (IVTBASE resets to 0x0008) |
| 97 | 0x00C8 | U4RX | __interrupt(irq(U4RX)) | UART2 Receive Interrupt; IRQ 96, vector table entry IVTBASE + 0xC0 (IVTBASE resets to 0x0008) |
| 98 | 0x00CA | U4TX | __interrupt(irq(U4TX)) | UART 4 Transmit Interrupt; IRQ 97, vector table entry IVTBASE + 0xC2 (IVTBASE resets to 0x0008) |
| 99 | 0x00CC | U4E | __interrupt(irq(U4E)) | UART4 Error Interrupt; IRQ 98, vector table entry IVTBASE + 0xC4 (IVTBASE resets to 0x0008) |
| 100 | 0x00CE | U4 | __interrupt(irq(U4)) | UART4 Interrupt; IRQ 99, vector table entry IVTBASE + 0xC6 (IVTBASE resets to 0x0008) |
| 101 | 0x00D0 | DMA5SCNT | __interrupt(irq(DMA5SCNT)) | DMA5 Source Count Interrupt; IRQ 100, vector table entry IVTBASE + 0xC8 (IVTBASE resets to 0x0008) |
| 102 | 0x00D2 | DMA5DCNT | __interrupt(irq(DMA5DCNT)) | DMA5 Destination Count Interrupt; IRQ 101, vector table entry IVTBASE + 0xCA (IVTBASE resets to 0x0008) |
| 103 | 0x00D4 | DMA5OR | __interrupt(irq(DMA5OR)) | DMA5 Overflow Interrupt; IRQ 102, vector table entry IVTBASE + 0xCC (IVTBASE resets to 0x0008) |
| 104 | 0x00D6 | DMA5A | __interrupt(irq(DMA5A)) | DMA5 Abort Interrupt; IRQ 103, vector table entry IVTBASE + 0xCE (IVTBASE resets to 0x0008) |
| 105 | 0x00D8 | U5RX | __interrupt(irq(U5RX)) | UART5 Receive Interrupt; IRQ 104, vector table entry IVTBASE + 0xD0 (IVTBASE resets to 0x0008) |
| 106 | 0x00DA | U5TX | __interrupt(irq(U5TX)) | UART5 Transmit Interrupt; IRQ 105, vector table entry IVTBASE + 0xD2 (IVTBASE resets to 0x0008) |
| 107 | 0x00DC | U5E | __interrupt(irq(U5E)) | UART5 Error Interrupt; IRQ 106, vector table entry IVTBASE + 0xD4 (IVTBASE resets to 0x0008) |
| 108 | 0x00DE | U5 | __interrupt(irq(U5)) | UART5 Interrupt; IRQ 107, vector table entry IVTBASE + 0xD6 (IVTBASE resets to 0x0008) |
| 109 | 0x00E0 | DMA6SCNT | __interrupt(irq(DMA6SCNT)) | DMA6 Source Count Interrupt; IRQ 108, vector table entry IVTBASE + 0xD8 (IVTBASE resets to 0x0008) |
| 110 | 0x00E2 | DMA6DCNT | __interrupt(irq(DMA6DCNT)) | DMA6 Destination Count Interrupt; IRQ 109, vector table entry IVTBASE + 0xDA (IVTBASE resets to 0x0008) |
| 111 | 0x00E4 | DMA6OR | __interrupt(irq(DMA6OR)) | DMA6 Overflow Interrupt; IRQ 110, vector table entry IVTBASE + 0xDC (IVTBASE resets to 0x0008) |
| 112 | 0x00E6 | DMA6A | __interrupt(irq(DMA6A)) | DMA6 Abort Interrupt; IRQ 111, vector table entry IVTBASE + 0xDE (IVTBASE resets to 0x0008) |
| 114 | 0x00EA | CLC7 | __interrupt(irq(CLC7)) | CLC7 Interrupt; IRQ 113, vector table entry IVTBASE + 0xE2 (IVTBASE resets to 0x0008) |
| 115 | 0x00EC | CM2 | __interrupt(irq(CM2)) | Comparator 2 Interrupt; IRQ 114, vector table entry IVTBASE + 0xE4 (IVTBASE resets to 0x0008) |
| 116 | 0x00EE | NCO3 | __interrupt(irq(NCO3)) | NCO3 Interrupt; IRQ 115, vector table entry IVTBASE + 0xE6 (IVTBASE resets to 0x0008) |
| 117 | 0x00F0 | DMA7SCNT | __interrupt(irq(DMA7SCNT)) | DMA7 Source Count Interrupt; IRQ 116, vector table entry IVTBASE + 0xE8 (IVTBASE resets to 0x0008) |
| 118 | 0x00F2 | DMA7DCNT | __interrupt(irq(DMA7DCNT)) | DMA7 Destination Count Interrupt; IRQ 117, vector table entry IVTBASE + 0xEA (IVTBASE resets to 0x0008) |
| 119 | 0x00F4 | DMA7OR | __interrupt(irq(DMA7OR)) | DMA7 Overflow Interrupt; IRQ 118, vector table entry IVTBASE + 0xEC (IVTBASE resets to 0x0008) |
| 120 | 0x00F6 | DMA7A | __interrupt(irq(DMA7A)) | DMA7 Abort Interrupt; IRQ 119, vector table entry IVTBASE + 0xEE (IVTBASE resets to 0x0008) |
| 121 | 0x00F8 | NVM | __interrupt(irq(NVM)) | NVM Interrupt; IRQ 120, vector table entry IVTBASE + 0xF0 (IVTBASE resets to 0x0008) |
| 122 | 0x00FA | CLC8 | __interrupt(irq(CLC8)) | CLC8 Interrupt; IRQ 121, vector table entry IVTBASE + 0xF2 (IVTBASE resets to 0x0008) |
| 123 | 0x00FC | CRC | __interrupt(irq(CRC)) | CRC Interrupt; IRQ 122, vector table entry IVTBASE + 0xF4 (IVTBASE resets to 0x0008) |
| 124 | 0x00FE | TMR6 | __interrupt(irq(TMR6)) | TMR6 Interrupt; IRQ 123, vector table entry IVTBASE + 0xF6 (IVTBASE resets to 0x0008) |
| 125 | 0x0100 | DMA8SCNT | __interrupt(irq(DMA8SCNT)) | DMA8 Source Count Interrupt; IRQ 124, vector table entry IVTBASE + 0xF8 (IVTBASE resets to 0x0008) |
| 126 | 0x0102 | DMA8DCNT | __interrupt(irq(DMA8DCNT)) | DMA8 Destination Count Interrupt; IRQ 125, vector table entry IVTBASE + 0xFA (IVTBASE resets to 0x0008) |
| 127 | 0x0104 | DMA8OR | __interrupt(irq(DMA8OR)) | DMA8 Overflow Interrupt; IRQ 126, vector table entry IVTBASE + 0xFC (IVTBASE resets to 0x0008) |
| 128 | 0x0106 | DMA8A | __interrupt(irq(DMA8A)) | DMA8 Abort Interrupt; IRQ 127, vector table entry IVTBASE + 0xFE (IVTBASE resets to 0x0008) |