PIC18F442 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0x27 default 0x27 OSCS Oscillator System Clock Switch Enable bit Oscillator system clock switch option is enabled (oscillator switching is enabled) Oscillator system clock switch option is disabled (main oscillator is source) OSC Oscillator Selection bits LP oscillator XT oscillator HS oscillator RC oscillator EC oscillator w/ OSC2 configured as divide-by-4 clock output EC oscillator w/ OSC2 configured as RA6 HS oscillator with PLL enabled/Clock frequency = (4 x FOSC) RC oscillator w/ OSC2 configured as RA6 CONFIG2L · 0x300002 0x0F default 0x0F BORV Brown-out Reset Voltage bits VBOR set to 4.5V VBOR set to 4.2V VBOR set to 2.7V VBOR set to 2.0V BOR Brown-out Reset Enable bit Brown-out Reset disabled Brown-out Reset enabled PWRT Power-up Timer Enable bit PWRT enabled PWRT disabled CONFIG2H · 0x300003 0x0F default 0x0F WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 WDT Watchdog Timer Enable bit WDT disabled (control is placed on the SWDTEN bit) WDT enabled CONFIG3H · 0x300005 0x01 default 0x01 CCP2MUX CCP2 Mux bit CCP2 input/output is multiplexed with RB3 CCP2 input/output is multiplexed with RC1 CONFIG4L · 0x300006 0x85 default 0x85 DEBUG Background Debugger Enable bit Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins. LVP Low Voltage ICSP Enable bit Low Voltage ICSP disabled Low Voltage ICSP enabled STVR Stack Full/Underflow Reset Enable bit Stack Full/Underflow will not cause RESET Stack Full/Underflow will cause RESET CONFIG5L · 0x300008 0x0F default 0x0F CP1 Code Protection bit Block 1 (002000-003FFFh) code protected Block 1 (002000-003FFFh) not code protected CP0 Code Protection bit Block 0 (000200-001FFFh) code protected Block 0 (000200-001FFFh) not code protected CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EEPROM Code Protection bit Data EEPROM code protected Data EEPROM not code protected CPB Boot Block Code Protection bit Boot Block (000000-0001FFh) code protected Boot Block (000000-0001FFh) not code protected CONFIG6L · 0x30000A 0x0F default 0x0F WRT1 Write Protection bit Block 1 (002000-003FFFh) write protected Block 1 (002000-003FFFh) not write protected WRT0 Write Protection bit Block 0 (000200-001FFFh) write protected Block 0 (000200-001FFFh) not write protected CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EEPROM Write Protection bit Data EEPROM write protected Data EEPROM not write protected WRTB Boot Block Write Protection bit Boot Block (000000-0001FFh) write protected Boot Block (000000-0001FFh) not write protected WRTC Configuration Register Write Protection bit Configuration registers (300000-3000FFh) write protected Configuration registers (300000-3000FFh) not write protected CONFIG7L · 0x30000C 0x0F default 0x0F EBTR1 Table Read Protection bit Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks EBTR0 Table Read Protection bit Block 0 (000200-001FFFh) protected from Table Reads executed in other blocks Block 0 (000200-001FFFh) not protected from Table Reads executed in other blocks CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Boot Block Table Read Protection bit Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks 
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