PIC18F46K80 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1L · 0x300000 0x5D default 0x5D XINST Extended Instruction Set Disabled Enabled SOSCSEL SOSC Power Selection and mode Configuration bits Low Power SOSC circuit selected Digital (SCLKI) mode High Power SOSC circuit selected INTOSCSEL LF-INTOSC Low-power Enable bit LF-INTOSC in Low-power mode during Sleep LF-INTOSC in High-power mode during Sleep RETEN VREG Sleep Enable bit Ultra low-power regulator is Enabled (Controlled by SRETEN bit) Ultra low-power regulator is Disabled (Controlled by REGSLP bit) CONFIG1H · 0x300001 0x08 default 0x08 IESO Internal External Oscillator Switch Over Mode Disabled Enabled FCMEN Fail-Safe Clock Monitor Disabled Enabled PLLCFG PLL x4 Enable bit Disabled Enabled FOSC Oscillator LP oscillator XT oscillator HS oscillator (High power, 16 MHz - 25 MHz) HS oscillator (Medium power, 4 MHz - 16 MHz) EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) EC oscillator (High power, 16 MHz - 64 MHz) External RC oscillator, CLKOUT function on OSC2 External RC oscillator Internal RC oscillator Internal RC oscillator, CLKOUT function on OSC2 EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 16 MHz) EC oscillator (Medium power, 160 kHz - 16 MHz) EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) EC oscillator (Low power, DC - 160 kHz) CONFIG2L · 0x300002 0x7F default 0x7F BORPWR BORMV Power level BORMV set to low power level BORMV set to medium power level BORMV set to high power level ZPBORMV instead of BORMV is selected BORV Brown-out Reset Voltage bits 3.0V 2.7V 2.0V 1.8V BOREN Brown Out Detect Disabled in hardware, SBOREN disabled Controlled with SBOREN bit Enabled while active, disabled in SLEEP, SBOREN disabled Enabled in hardware, SBOREN disabled PWRTEN Power Up Timer Enabled Disabled CONFIG2H · 0x300003 0x7F default 0x7F WDTPS Watchdog Postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 31 (not named) WDTEN Watchdog Timer WDT disabled in hardware; SWDTEN bit disabled WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled WDT controlled by SWDTEN bit setting WDT enabled in hardware; SWDTEN bit disabled CONFIG3H · 0x300005 0x89 default 0x89 MCLRE Master Clear Enable MCLR Disabled, RE3 Enabled MCLR Enabled, RE3 Disabled MSSPMSK MSSP address masking 5 bit address masking mode 7 Bit address masking mode CANMX ECAN Mux bit ECAN TX and RX pins are located on RC6 and RC7, respectively ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG4L · 0x300006 0x91 default 0x91 DEBUG Background Debugger Background Debugger enabled Background Debugger disabled BBSIZ Boot Block Size 1K word Boot Block size 2K word Boot Block size STVREN Stack Overflow Reset Disabled Enabled CONFIG5L · 0x300008 0x0F default 0x0F CP3 Code Protect 0C000-0FFFF Enabled Disabled CP2 Code Protect 08000-0BFFF Enabled Disabled CP1 Code Protect 04000-07FFF Enabled Disabled CP0 Code Protect 00800-03FFF Enabled Disabled CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EE Read Protect Enabled Disabled CPB Code Protect Boot Enabled Disabled CONFIG6L · 0x30000A 0x0F default 0x0F WRT3 Table Write Protect 0C000-0FFFF Enabled Disabled WRT2 Table Write Protect 08000-0BFFF Enabled Disabled WRT1 Table Write Protect 04000-07FFF Enabled Disabled WRT0 Table Write Protect 00800-03FFF Enabled Disabled CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EE Write Protect Enabled Disabled WRTB Table Write Protect Boot Enabled Disabled WRTC Config. Write Protect Enabled Disabled CONFIG7L · 0x30000C 0x0F default 0x0F EBTR3 Table Read Protect 0C000-0FFFF Enabled Disabled EBTR2 Table Read Protect 08000-0BFFF Enabled Disabled EBTR1 Table Read Protect 04000-07FFF Enabled Disabled EBTR0 Table Read Protect 00800-03FFF Enabled Disabled CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Table Read Protect Boot Enabled Disabled 
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