PIC18F67J50 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1L · 0x1FFF8 0xEF default 0xEF DEBUG Background Debugger Enable bit Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins XINST Extended Instruction Set Enable bit Instruction set extension and Indexed Addressing mode disabled (Legacy mode) Instruction set extension and Indexed Addressing mode enabled STVREN Stack Overflow/Underflow Reset Enable bit Reset on stack overflow/underflow disabled Reset on stack overflow/underflow enabled PLLDIV PLL Prescaler Selection bits Divide by 12 (48 MHz oscillator input) Divide by 10 (40 MHz oscillator input) Divide by 6 (24 MHz oscillator input) Divide by 5 (20 MHz oscillator input) Divide by 4 (16 MHz oscillator input) Divide by 3 (12 MHz oscillator input) Divide by 2 (8 MHz oscillator input) No prescale (4 MHz oscillator input drives PLL directly) WDTEN Watchdog Timer Enable bit WDT disabled (control is placed on SWDTEN bit) WDT enabled CONFIG1H · 0x1FFF9 0xF7 default 0xF7 RESERVED RESERVED SIGN Config Word Signature Bit 1 · unprogrammed 0 · programmed CP0 Code Protection bit Program memory is code-protected Program memory is not code-protected CPUDIV CPU System Clock Postscaler CPU system clock divide by 6 CPU system clock divide by 3 CPU system clock divide by 2 No CPU system clock divide CONFIG2L · 0x1FFFA 0xC7 default 0xC7 IESO Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit Two-Speed Start-up disabled Two-Speed Start-up enabled FCMEN Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled FOSC Oscillator Selection bits INTOSC, Port function on RA6 and RA7 INTOSC, CLKO on RA6 and Port function on RA7 INTOSC with PLL enabled, Port function on RA6 and RA7 INTOSC with PLL enabled, CLKO on RA6 and Port function on RA7 HS oscillator, HS used by USB HS oscillator, PLL enabled, HSPLL used by USB EC Oscillator with CLKO on RA6, EC used by USB EC Oscillator with PLL, CLKO on RA6, ECPLL used by USB CONFIG2H · 0x1FFFB 0xFF default 0xFF RESERVED RESERVED WDTPS Watchdog Timer Postscaler Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 CONFIG3L · 0x1FFFC 0xF8 default 0xF8 RESERVED RESERVED CONFIG3H · 0x1FFFD 0xF9 default 0xF9 RESERVED RESERVED MSSPMSK MSSP Address Masking Mode Select bit 5-Bit Address Masking mode enable 7-Bit Address Masking mode enable RES RESERVED 1 · unprogrammed 0 · programmed CCP2MX ECCP2 MUX bit ECCP2/P2A is multiplexed with RE7 ECCP2/P2A is multiplexed with RC1 
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