PIC18F8621 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0x2F default 0x2F OSCS Oscillator System Clock Switch Enable bit Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) Oscillator system clock switch option is disabled (main oscillator is source) OSC Oscillator Selection bits LP oscillator XT oscillator HS oscillator RC oscillator with OSC2 configured as divide by 4 clock output EC oscillator with OSC2 configured as divide by 4 clock output EC oscillator with OSC2 configured as RA6 HS oscillator with HW enabled 4x PLL RC oscillator with OSC2 configured as RA6 EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL HS oscillator with SW enabled 4x PLL 15 (not named) CONFIG2L · 0x300002 0x0F default 0x0F BORV Brown-out Reset Voltage bits VBOR set to 4.5V VBOR set to 4.2V VBOR set to 2.7V VBOR set to 2.0V BOR Brown-out Reset Enable bit Brown-out Reset disabled Brown-out Reset enabled PWRT Power-up Timer Enable bit PWRT enabled PWRT disabled CONFIG2H · 0x300003 0x1F default 0x1F WDTPS Watchdog Timer Postscaler Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 WDT Watchdog Timer Enable bit WDT disabled (control is placed on the SWDTEN bit) WDT enabled CONFIG3L · 0x300004 0x83 default 0x83 WAIT External Bus Data Wait Enable bit Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) Wait selections unavailable for table reads and table writes MODE Processor Mode Select bits Extended Microcontroller mode Microprocessor with Boot Block mode Microprocessor mode Microcontroller mode CONFIG3H · 0x300005 0x83 default 0x83 MCLRE MCLR Enable bit RG5 input enabled, MCLR disabled MCLR pin enabled, RG5 input pin disabled ECCPMX ECCP Mux bit ECCP1 (P1B/P1C) and ECCP3 (P3B/P3C) PWM outputs are multiplexed with RH7 through RH4 ECCP1 (P1B/P1C) and ECCP3 (P3B/P3C) PWM outputs are multiplexed with RE6 through RE3 CCP2MX ECCP2 Mux bit Multiplexed with RB3 or RE7 Multiplexed with RC1 CONFIG4L · 0x300006 0x85 default 0x85 DEBUG Background Debugger Enable bit Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. LVP Low-Voltage ICSP Enable bit Low-Voltage ICSP disabled Low-Voltage ICSP enabled STVR Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset CONFIG5L · 0x300008 0x0F default 0x0F CP3 Code Protection bit Block 3 (00C000-00FFFFh) code-protected Block 3 (00C000-00FFFFh) not code-protected CP2 Code Protection bit Block 2 (008000-00BFFFh) code-protected Block 2 (008000-00BFFFh) not code-protected CP1 Code Protection bit Block 1 (004000-007FFFh) code-protected Block 1 (004000-007FFFh) not code-protected CP0 Code Protection bit Block 0 (000800-003FFFh) code-protected Block 0 (000800-003FFFh) not code-protected CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EEPROM Code Protection bit Data EEPROM code-protected Data EEPROM not code-protected CPB Boot Block Code Protection bit Boot block (000000-0007FFh) code-protected Boot block (000000-0007FFh) not code-protected CONFIG6L · 0x30000A 0x0F default 0x0F WRT3 Write Protection bit Block 3 (00C000-00FFFFh) write-protected Block 3 (00C000-00FFFFh) not write-protected WRT2 Write Protection bit Block 2 (008000-00BFFFh) write-protected Block 2 (008000-00BFFFh) not write-protected WRT1 Write Protection bit Block 1 (004000-007FFFh) write-protected Block 1 (004000-007FFFh) not write-protected WRT0 Write Protection bit Block 0 (000800-003FFFh) write-protected Block 0 (000800-003FFFh) not write-protected CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EEPROM Write Protection bit Data EEPROM write-protected Data EEPROM not write-protected WRTB Boot Block Write Protection bit Boot block (000000-0007FFh) write-protected Boot block (000000-0007FFh) not write-protected WRTC Configuration Register Write Protection bit Configuration registers (300000-3000FFh) write-protected Configuration registers (300000-3000FFh) not write-protected CONFIG7L · 0x30000C 0x0F default 0x0F EBTR3 Table Read Protection bit Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks EBTR2 Table Read Protection bit Block 2 (008000-00BFFFh) protected from table reads executed in other blocks Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks EBTR1 Table Read Protection bit Block 1 (004000-007FFFh) protected from table reads executed in other blocks Block 1 (004000-007FFFh) not protected from table reads executed in other blocks EBTR0 Table Read Protection bit Block 0 (000800-003FFFh) protected from table reads executed in other blocks Block 0 (000800-003FFFh) not protected from table reads executed in other blocks CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Boot Block Table Read Protection bit Boot block (000000-0007FFh) protected from table reads executed in other blocks Boot block (000000-0007FFh) not protected from table reads executed in other blocks 
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