BETAPIC18LF26K42 interrupt vectors
Reset at 0x0000, then a vector table of 68 sources: each source's entry is at IVTBASE + 2 × its IRQ number (IVTBASE is 0x0008 after reset) and holds its handler's address. With MVECEN off the chip uses 0x0008 and 0x0018 as the other PIC18s do. Each source has an enable bit and a flag (the Registers page lists them). In XC8 a handler is void __interrupt(irq(TMR0)) isr(void).
| Vector | Program address | Name | Handler | Source |
|---|---|---|---|---|
| 0 | 0x0000 | RESET | reset: main() after start-up | Reset vector, address 0x0000 |
| 1 | 0x0008 | SWINT | __interrupt(irq(SWINT)) | Software Interrupt; IRQ 0, vector table entry IVTBASE + 0x00 (IVTBASE resets to 0x0008) |
| 2 | 0x000A | HLVD | __interrupt(irq(HLVD)) | HLVD Interrupt; IRQ 1, vector table entry IVTBASE + 0x02 (IVTBASE resets to 0x0008) |
| 3 | 0x000C | OSF | __interrupt(irq(OSF)) | Oscillator Failure Interrupt; IRQ 2, vector table entry IVTBASE + 0x04 (IVTBASE resets to 0x0008) |
| 4 | 0x000E | CSW | __interrupt(irq(CSW)) | Clock Switch Interrupt; IRQ 3, vector table entry IVTBASE + 0x06 (IVTBASE resets to 0x0008) |
| 5 | 0x0010 | NVM | __interrupt(irq(NVM)) | NVM Interrupt; IRQ 4, vector table entry IVTBASE + 0x08 (IVTBASE resets to 0x0008) |
| 6 | 0x0012 | SCAN | __interrupt(irq(SCAN)) | Scanner Interrupt; IRQ 5, vector table entry IVTBASE + 0x0A (IVTBASE resets to 0x0008) |
| 7 | 0x0014 | CRC | __interrupt(irq(CRC)) | CRC Interrupt; IRQ 6, vector table entry IVTBASE + 0x0C (IVTBASE resets to 0x0008) |
| 8 | 0x0016 | IOC | __interrupt(irq(IOC)) | Interrupt on change; IRQ 7, vector table entry IVTBASE + 0x0E (IVTBASE resets to 0x0008) |
| 9 | 0x0018 | INT0 | __interrupt(irq(INT0)) | External Interrupt 0; IRQ 8, vector table entry IVTBASE + 0x10 (IVTBASE resets to 0x0008) |
| 10 | 0x001A | ZCD | __interrupt(irq(ZCD)) | ZCD Interrupt; IRQ 9, vector table entry IVTBASE + 0x12 (IVTBASE resets to 0x0008) |
| 11 | 0x001C | AD | __interrupt(irq(AD)) | ADC Interrupt; IRQ 10, vector table entry IVTBASE + 0x14 (IVTBASE resets to 0x0008) |
| 12 | 0x001E | ADT | __interrupt(irq(ADT)) | ADC Treshold Interrupt; IRQ 11, vector table entry IVTBASE + 0x16 (IVTBASE resets to 0x0008) |
| 13 | 0x0020 | CMP1 | __interrupt(irq(CMP1)) | Comparator 1 Interrupt; IRQ 12, vector table entry IVTBASE + 0x18 (IVTBASE resets to 0x0008) |
| 14 | 0x0022 | SMT1 | __interrupt(irq(SMT1)) | SMT1 Interrupt; IRQ 13, vector table entry IVTBASE + 0x1A (IVTBASE resets to 0x0008) |
| 15 | 0x0024 | SMT1PRA | __interrupt(irq(SMT1PRA)) | SMT1 Period acqusition Interrupt; IRQ 14, vector table entry IVTBASE + 0x1C (IVTBASE resets to 0x0008) |
| 16 | 0x0026 | SMT1PRW | __interrupt(irq(SMT1PRW)) | SMT1 Pulse width acqusition Interrupt; IRQ 15, vector table entry IVTBASE + 0x1E (IVTBASE resets to 0x0008) |
| 17 | 0x0028 | DMA1SCNT | __interrupt(irq(DMA1SCNT)) | DMA1 Source count Interrupt; IRQ 16, vector table entry IVTBASE + 0x20 (IVTBASE resets to 0x0008) |
| 18 | 0x002A | DMA1DCNT | __interrupt(irq(DMA1DCNT)) | DMA1 Destination count Interrupt; IRQ 17, vector table entry IVTBASE + 0x22 (IVTBASE resets to 0x0008) |
| 19 | 0x002C | DMA1OR | __interrupt(irq(DMA1OR)) | DMA1 Overflow Interrupt; IRQ 18, vector table entry IVTBASE + 0x24 (IVTBASE resets to 0x0008) |
| 20 | 0x002E | DMA1A | __interrupt(irq(DMA1A)) | DMA1 Abort Interrupt; IRQ 19, vector table entry IVTBASE + 0x26 (IVTBASE resets to 0x0008) |
| 21 | 0x0030 | SPI1RX | __interrupt(irq(SPI1RX)) | SPI1 Receive Interrupt; IRQ 20, vector table entry IVTBASE + 0x28 (IVTBASE resets to 0x0008) |
| 22 | 0x0032 | SPI1TX | __interrupt(irq(SPI1TX)) | SPI1 Transmit Interrupt; IRQ 21, vector table entry IVTBASE + 0x2A (IVTBASE resets to 0x0008) |
| 23 | 0x0034 | SPI1 | __interrupt(irq(SPI1)) | SPI1 Interrupt; IRQ 22, vector table entry IVTBASE + 0x2C (IVTBASE resets to 0x0008) |
| 24 | 0x0036 | I2C1RX | __interrupt(irq(I2C1RX)) | I2C1 Receive Interrupt; IRQ 23, vector table entry IVTBASE + 0x2E (IVTBASE resets to 0x0008) |
| 25 | 0x0038 | I2C1TX | __interrupt(irq(I2C1TX)) | I2C1 Transmit Interrupt; IRQ 24, vector table entry IVTBASE + 0x30 (IVTBASE resets to 0x0008) |
| 26 | 0x003A | I2C1 | __interrupt(irq(I2C1)) | I2C1 Interrupt; IRQ 25, vector table entry IVTBASE + 0x32 (IVTBASE resets to 0x0008) |
| 27 | 0x003C | I2C1E | __interrupt(irq(I2C1E)) | I2C1 Error Interrupt; IRQ 26, vector table entry IVTBASE + 0x34 (IVTBASE resets to 0x0008) |
| 28 | 0x003E | U1RX | __interrupt(irq(U1RX)) | UART1 Receive Interrupt; IRQ 27, vector table entry IVTBASE + 0x36 (IVTBASE resets to 0x0008) |
| 29 | 0x0040 | U1TX | __interrupt(irq(U1TX)) | UART1 Transmit Interrupt; IRQ 28, vector table entry IVTBASE + 0x38 (IVTBASE resets to 0x0008) |
| 30 | 0x0042 | U1E | __interrupt(irq(U1E)) | UART1 Error Interrupt; IRQ 29, vector table entry IVTBASE + 0x3A (IVTBASE resets to 0x0008) |
| 31 | 0x0044 | U1 | __interrupt(irq(U1)) | UART1 Interrupt; IRQ 30, vector table entry IVTBASE + 0x3C (IVTBASE resets to 0x0008) |
| 32 | 0x0046 | TMR0 | __interrupt(irq(TMR0)) | Timer0 Interrupt; IRQ 31, vector table entry IVTBASE + 0x3E (IVTBASE resets to 0x0008) |
| 33 | 0x0048 | TMR1 | __interrupt(irq(TMR1)) | Timer1 Interrupt; IRQ 32, vector table entry IVTBASE + 0x40 (IVTBASE resets to 0x0008) |
| 34 | 0x004A | TMR1G | __interrupt(irq(TMR1G)) | Timer1 Gate Interrupt; IRQ 33, vector table entry IVTBASE + 0x42 (IVTBASE resets to 0x0008) |
| 35 | 0x004C | TMR2 | __interrupt(irq(TMR2)) | Timer2 Interrupt; IRQ 34, vector table entry IVTBASE + 0x44 (IVTBASE resets to 0x0008) |
| 36 | 0x004E | CCP1 | __interrupt(irq(CCP1)) | CCP1 Interrupt; IRQ 35, vector table entry IVTBASE + 0x46 (IVTBASE resets to 0x0008) |
| 38 | 0x0052 | NCO1 | __interrupt(irq(NCO1)) | NCO1 Interrupt; IRQ 37, vector table entry IVTBASE + 0x4A (IVTBASE resets to 0x0008) |
| 39 | 0x0054 | CWG1 | __interrupt(irq(CWG1)) | CWG1 Interrupt; IRQ 38, vector table entry IVTBASE + 0x4C (IVTBASE resets to 0x0008) |
| 40 | 0x0056 | CLC1 | __interrupt(irq(CLC1)) | CLC1 Interrupt; IRQ 39, vector table entry IVTBASE + 0x4E (IVTBASE resets to 0x0008) |
| 41 | 0x0058 | INT1 | __interrupt(irq(INT1)) | External Interrupt 1; IRQ 40, vector table entry IVTBASE + 0x50 (IVTBASE resets to 0x0008) |
| 42 | 0x005A | CMP2 | __interrupt(irq(CMP2)) | Comparator 2 Interrupt; IRQ 41, vector table entry IVTBASE + 0x52 (IVTBASE resets to 0x0008) |
| 43 | 0x005C | DMA2SCNT | __interrupt(irq(DMA2SCNT)) | DMA2 Source count Interrupt; IRQ 42, vector table entry IVTBASE + 0x54 (IVTBASE resets to 0x0008) |
| 44 | 0x005E | DMA2DCNT | __interrupt(irq(DMA2DCNT)) | DMA2 Destination count Interrupt; IRQ 43, vector table entry IVTBASE + 0x56 (IVTBASE resets to 0x0008) |
| 45 | 0x0060 | DMA2OR | __interrupt(irq(DMA2OR)) | DMA2 Overflow Interrupt; IRQ 44, vector table entry IVTBASE + 0x58 (IVTBASE resets to 0x0008) |
| 46 | 0x0062 | DMA2A | __interrupt(irq(DMA2A)) | DMA2 Abort Interrupt; IRQ 45, vector table entry IVTBASE + 0x5A (IVTBASE resets to 0x0008) |
| 47 | 0x0064 | I2C2RX | __interrupt(irq(I2C2RX)) | I2C2 Receive Interrupt; IRQ 46, vector table entry IVTBASE + 0x5C (IVTBASE resets to 0x0008) |
| 48 | 0x0066 | I2C2TX | __interrupt(irq(I2C2TX)) | I2C2 Transmit Interrupt; IRQ 47, vector table entry IVTBASE + 0x5E (IVTBASE resets to 0x0008) |
| 49 | 0x0068 | I2C2 | __interrupt(irq(I2C2)) | I2C2 Interrupt; IRQ 48, vector table entry IVTBASE + 0x60 (IVTBASE resets to 0x0008) |
| 50 | 0x006A | I2C2E | __interrupt(irq(I2C2E)) | I2C2 Error Interrupt; IRQ 49, vector table entry IVTBASE + 0x62 (IVTBASE resets to 0x0008) |
| 51 | 0x006C | U2RX | __interrupt(irq(U2RX)) | UART2 Receive Interrupt; IRQ 50, vector table entry IVTBASE + 0x64 (IVTBASE resets to 0x0008) |
| 52 | 0x006E | U2TX | __interrupt(irq(U2TX)) | UART2 Transmit Interrupt; IRQ 51, vector table entry IVTBASE + 0x66 (IVTBASE resets to 0x0008) |
| 53 | 0x0070 | U2E | __interrupt(irq(U2E)) | UART2 Error Interrupt; IRQ 52, vector table entry IVTBASE + 0x68 (IVTBASE resets to 0x0008) |
| 54 | 0x0072 | U2 | __interrupt(irq(U2)) | UART2 Interrupt; IRQ 53, vector table entry IVTBASE + 0x6A (IVTBASE resets to 0x0008) |
| 55 | 0x0074 | TMR3 | __interrupt(irq(TMR3)) | Timer3 Interrupt; IRQ 54, vector table entry IVTBASE + 0x6C (IVTBASE resets to 0x0008) |
| 56 | 0x0076 | TMR3G | __interrupt(irq(TMR3G)) | Timer3 Gate Interrupt; IRQ 55, vector table entry IVTBASE + 0x6E (IVTBASE resets to 0x0008) |
| 57 | 0x0078 | TMR4 | __interrupt(irq(TMR4)) | Timer4 Interrupt; IRQ 56, vector table entry IVTBASE + 0x70 (IVTBASE resets to 0x0008) |
| 58 | 0x007A | CCP2 | __interrupt(irq(CCP2)) | CCP2 Interrupt; IRQ 57, vector table entry IVTBASE + 0x72 (IVTBASE resets to 0x0008) |
| 60 | 0x007E | CWG2 | __interrupt(irq(CWG2)) | CWG2 Interrupt; IRQ 59, vector table entry IVTBASE + 0x76 (IVTBASE resets to 0x0008) |
| 61 | 0x0080 | CLC2 | __interrupt(irq(CLC2)) | CLC2 Interrupt; IRQ 60, vector table entry IVTBASE + 0x78 (IVTBASE resets to 0x0008) |
| 62 | 0x0082 | INT2 | __interrupt(irq(INT2)) | External Interrupt 2; IRQ 61, vector table entry IVTBASE + 0x7A (IVTBASE resets to 0x0008) |
| 71 | 0x0094 | TMR5 | __interrupt(irq(TMR5)) | Timer5 Interrupt; IRQ 70, vector table entry IVTBASE + 0x8C (IVTBASE resets to 0x0008) |
| 72 | 0x0096 | TMR5G | __interrupt(irq(TMR5G)) | Timer5 Gate Interrupt; IRQ 71, vector table entry IVTBASE + 0x8E (IVTBASE resets to 0x0008) |
| 73 | 0x0098 | TMR6 | __interrupt(irq(TMR6)) | Timer6 Interrupt; IRQ 72, vector table entry IVTBASE + 0x90 (IVTBASE resets to 0x0008) |
| 74 | 0x009A | CCP3 | __interrupt(irq(CCP3)) | CCP3 Interrupt; IRQ 73, vector table entry IVTBASE + 0x92 (IVTBASE resets to 0x0008) |
| 75 | 0x009C | CWG3 | __interrupt(irq(CWG3)) | CWG3 Interrupt; IRQ 74, vector table entry IVTBASE + 0x94 (IVTBASE resets to 0x0008) |
| 76 | 0x009E | CLC3 | __interrupt(irq(CLC3)) | CLC3 Interrupt; IRQ 75, vector table entry IVTBASE + 0x96 (IVTBASE resets to 0x0008) |
| 81 | 0x00A8 | CCP4 | __interrupt(irq(CCP4)) | CCP4 Interrupt; IRQ 80, vector table entry IVTBASE + 0xA0 (IVTBASE resets to 0x0008) |
| 82 | 0x00AA | CLC4 | __interrupt(irq(CLC4)) | CLC4 Interrupt; IRQ 81, vector table entry IVTBASE + 0xA2 (IVTBASE resets to 0x0008) |