PIC18LF27K40 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1L · 0x300000 0xFF default 0xFF RSTOSC Power-up default value for COSC bits HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1 Reserved EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits Reserved Secondary Oscillator Low-Frequency Oscillator HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1 EXTOSC operating per FEXTOSC bits (device manufacturing default) FEXTOSC External Oscillator mode Selection bits LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power XT (crystal oscillator) above 100 kHz, below 8 MHz; PFM set to medium power HS (crystal oscillator) above 8 MHz; PFM set to high power Reserved (DO NOT USE) Oscillator not enabled EC (external clock) below 100 kHz; PFM set to low power EC (external clock) for 500 kHz to 8 MHz; PFM set to medium power EC (external clock) above 8 MHz; PFM set to high power CONFIG1H · 0x300001 0xFF default 0xFF FCMEN Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled CSWEN Clock Switch Enable bit The NOSC and NDIV bits cannot be changed by user software Writing to NOSC and NDIV is allowed CLKOUTEN Clock Out Enable bit CLKOUT function is enabled CLKOUT function is disabled CONFIG2L · 0x300002 0xFF default 0xFF BOREN Brown-out Reset Enable bits Brown-out Reset disabled Brown-out Reset enabled according to SBOREN Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored Brown-out Reset enabled , SBOREN bit is ignored LPBOREN Low-power BOR enable bit ULPBOR enabled ULPBOR disabled PWRTE Power-up Timer Enable bit Power up timer enabled Power up timer disabled MCLRE Master Clear Enable bit If LVP = 0, MCLR pin function is port defined function; If LVP =1, RE3 pin fuction is MCLR If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR CONFIG2H · 0x300003 0xFF default 0xFF XINST Extended Instruction Set Enable bit Extended Instruction Set and Indexed Addressing Mode enabled Extended Instruction Set and Indexed Addressing Mode disabled DEBUG Debugger Enable bit Background debugger enabled Background debugger disabled STVREN Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset PPS1WAY PPSLOCK bit One-Way Set Enable bit PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle ZCD ZCD Disable bit ZCD always enabled ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON BORV Brown Out Reset Voltage selection bits Brown-out Reset Voltage (VBOR) set to 2.85V Brown-out Reset Voltage (VBOR) set to 2.70V Brown-out Reset Voltage (VBOR) set to 2.45V Brown-out Reset Voltage (VBOR) set to 1.90V CONFIG3L · 0x300004 0xFF default 0xFF WDTE WDT operating mode WDT Disabled WDT enabled/disabled by SWDTEN bit WDT enabled while sleep=0, suspended when sleep=1 WDT enabled regardless of sleep WDTCPS WDT Period Select bits Divider ratio 1:32 Divider ratio 1:64 Divider ratio 1:128 Divider ratio 1:256 Divider ratio 1:512 Divider ratio 1:1024 Divider ratio 1:2048 Divider ratio 1:4096 Divider ratio 1:8192 Divider ratio 1:16384 Divider ratio 1:32768 Divider ratio 1:65536 Divider ratio 1:131072 Divider ratio 1:262144 Divider ratio 1:524299 Divider ratio 1:1048576 Divider ratio 1:2097152 Divider ratio 1:4194304 Divider ratio 1:8388608 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:65536; software control of WDTPS CONFIG3H · 0x300005 0xFF default 0xFF WDTCCS WDT input clock selector WDT reference clock is the 31.0 kHz LFINTOSC WDT reference clock is the 31.2kHz HFINTOSC output Software Control WDTCWS WDT Window Select bits window delay = 87.5; no software control; keyed access required window delay = 75 percent of time; no software control; keyed access required window delay = 62.5 percent of time; no software control; keyed access required window delay = 50 percent of time; no software control; keyed access required window delay = 37.5 percent of time; no software control; keyed access required window delay = 25 percent of time; no software control; keyed access required window always open (100%); no software control; keyed access required window always open (100%); software control; keyed access not required CONFIG4L · 0x300006 0xFF default 0xFF WRT7 Write Protection Block 7 Block 7 (01C000-01FFFFh) write-protected Block 7 (01C000-01FFFFh) not write-protected WRT6 Write Protection Block 6 Block 6 (018000-01BFFFh) write-protected Block 6 (018000-01BFFFh) not write-protected WRT5 Write Protection Block 5 Block 5 (014000-017FFFh) write-protected Block 5 (014000-017FFFh) not write-protected WRT4 Write Protection Block 4 Block 4 (010000-013FFFh) write-protected Block 4 (010000-013FFFh) not write-protected WRT3 Write Protection Block 3 Block 3 (00C000-00FFFFh) write-protected Block 3 (00C000-00FFFFh) not write-protected WRT2 Write Protection Block 2 Block 2 (008000-00BFFFh) write-protected Block 2 (008000-00BFFFh) not write-protected WRT1 Write Protection Block 1 Block 1 (004000-007FFFh) write-protected Block 1 (004000-007FFFh) not write-protected WRT0 Write Protection Block 0 Block 0 (000800-003FFFh) write-protected Block 0 (000800-003FFFh) not write-protected CONFIG4H · 0x300007 0xFF default 0xFF LVP Low Voltage Programming Enable bit HV on MCLR/VPP must be used for programming Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored SCANE Scanner Enable bit Scanner module is NOT available for use, SCANMD bit is ignored Scanner module is available for use, SCANMD bit can control the module WRTD Data EEPROM Write Protection bit Data EEPROM write-protected Data EEPROM not write-protected WRTB Boot Block Write Protection bit Boot Block (000000-0007FFh) write-protected Boot Block (000000-0007FFh) not write-protected WRTC Configuration Register Write Protection bit Configuration registers (300000-30000Bh) write-protected Configuration registers (300000-30000Bh) not write-protected CONFIG5L · 0x300008 0xFF default 0xFF CPD DataNVM Memory Code Protection bit DataNVM code protection enabled DataNVM code protection disabled CP UserNVM Program Memory Code Protection bit UserNVM code protection enabled UserNVM code protection disabled CONFIG5H · 0x300009 0xFF default 0xFF CONFIG5H CONFIG6L · 0x30000A 0xFF default 0xFF EBTR7 Table Read Protection Block 7 Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks EBTR6 Table Read Protection Block 6 Block 6 (018000-01BFFFh) protected from table reads executed in other blocks Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks EBTR5 Table Read Protection Block 5 Block 5 (014000-017FFFh) protected from table reads executed in other blocks Block 5 (014000-017FFFh) not protected from table reads executed in other blocks EBTR4 Table Read Protection Block 4 Block 4 (010000-013FFFh) protected from table reads executed in other blocks Block 4 (010000-013FFFh) not protected from table reads executed in other blocks EBTR3 Table Read Protection Block 3 Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks EBTR2 Table Read Protection Block 2 Block 2 (008000-00BFFFh) protected from table reads executed in other blocks Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks EBTR1 Table Read Protection Block 1 Block 1 (004000-007FFFh) protected from table reads executed in other blocks Block 1 (004000-007FFFh) not protected from table reads executed in other blocks EBTR0 Table Read Protection Block 0 Block 0 (000800-003FFFh) protected from table reads executed in other blocks Block 0 (000800-003FFFh) not protected from table reads executed in other blocks CONFIG6H · 0x30000B 0xFF default 0xFF EBTRB Boot Block Table Read Protection bit Boot Block (000000-0007FFh) protected from table reads executed in other blocks Boot Block (000000-0007FFh) not protected from table reads executed in other blocks 
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