PIC18LF43K22 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0x25 default 0x25 IESO Internal/External Oscillator Switchover bit Oscillator Switchover mode disabled Oscillator Switchover mode enabled FCMEN Fail-Safe Clock Monitor Enable bit Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled PRICLKEN Primary clock enable bit Primary clock can be disabled by software Primary clock is always enabled PLLCFG 4X PLL Enable Oscillator used directly Oscillator multiplied by 4 FOSC Oscillator Selection bits LP oscillator XT oscillator HS oscillator (high power > 16 MHz) HS oscillator (medium power 4-16 MHz) EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) EC oscillator (high power, >16 MHz) External RC oscillator, CLKOUT function on OSC2 External RC oscillator Internal oscillator block Internal oscillator block, CLKOUT function on OSC2 EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz) EC oscillator (medium power, 500 kHz-16 MHz) EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz) EC oscillator (low power, <500 kHz) 111X External RC oscillator, CLKOUT function on RA6 CONFIG2L · 0x300002 0x1F default 0x1F BORV Brown Out Reset Voltage bits VBOR set to 2.85 V nominal VBOR set to 2.50 V nominal VBOR set to 2.20 V nominal VBOR set to 1.90 V nominal BOREN Brown-out Reset Enable bits Brown-out Reset disabled in hardware and software Brown-out Reset enabled and controlled by software (SBOREN is enabled) Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) Brown-out Reset enabled in hardware only (SBOREN is disabled) PWRTEN Power-up Timer Enable bit Power up timer enabled Power up timer disabled CONFIG2H · 0x300003 0x3F default 0x3F WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 WDTEN Watchdog Timer Enable bits Watch dog timer is always disabled. SWDTEN has no effect. WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect WDT is controlled by SWDTEN bit of the WDTCON register WDT is always enabled. SWDTEN bit has no effect CONFIG3H · 0x300005 0xBF default 0xBF MCLRE MCLR Pin Enable bit RE3 input pin enabled; MCLR disabled MCLR pin enabled, RE3 input pin disabled P2BMX ECCP2 B output mux bit P2B is on RC0 P2B is on RD2 T3CMX Timer3 Clock input mux bit T3CKI is on RB5 T3CKI is on RC0 HFOFST HFINTOSC Fast Start-up HFINTOSC output and ready status are delayed by the oscillator stable status HFINTOSC output and ready status are not delayed by the oscillator stable status CCP3MX P3A/CCP3 Mux bit P3A/CCP3 input/output is mulitplexed with RE0 P3A/CCP3 input/output is multiplexed with RB5 PBADEN PORTB A/D Enable bit PORTB<5:0> pins are configured as digital I/O on Reset PORTB<5:0> pins are configured as analog input channels on Reset CCP2MUX CCP2 MUX bit CCP2 input/output is multiplexed with RB3 CCP2 input/output is multiplexed with RC1 CONFIG4L · 0x300006 0x85 default 0x85 DEBUG Background Debug Enabled Disabled XINST Extended Instruction Set Enable bit Instruction set extension and Indexed Addressing mode disabled (Legacy mode) Instruction set extension and Indexed Addressing mode enabled LVP Single-Supply ICSP Enable bit Single-Supply ICSP disabled Single-Supply ICSP enabled if MCLRE is also 1 STVREN Stack Full/Underflow Reset Enable bit Stack full/underflow will not cause Reset Stack full/underflow will cause Reset CONFIG5L · 0x300008 0x03 default 0x03 CP1 Code Protection Block 1 Block 1 (001000-001FFFh) code-protected Block 1 (001000-001FFFh) not code-protected CP0 Code Protection Block 0 Block 0 (000200-000FFFh) code-protected Block 0 (000200-000FFFh) not code-protected CONFIG5H · 0x300009 0xC0 default 0xC0 CPD Data EEPROM Code Protection bit Data EEPROM code-protected Data EEPROM not code-protected CPB Boot Block Code Protection bit Boot block (000000-0001FFh) code-protected Boot block (000000-0001FFh) not code-protected CONFIG6L · 0x30000A 0x03 default 0x03 WRT1 Write Protection Block 1 Block 1 (001000-001FFFh) write-protected Block 1 (001000-001FFFh) not write-protected WRT0 Write Protection Block 0 Block 0 (000200-000FFFh) write-protected Block 0 (000200-000FFFh) not write-protected CONFIG6H · 0x30000B 0xE0 default 0xE0 WRTD Data EEPROM Write Protection bit Data EEPROM write-protected Data EEPROM not write-protected WRTB Boot Block Write Protection bit Boot Block (000000-0001FFh) write-protected Boot Block (000000-0001FFh) not write-protected WRTC Configuration Register Write Protection bit Configuration registers (300000-3000FFh) write-protected Configuration registers (300000-3000FFh) not write-protected CONFIG7L · 0x30000C 0x03 default 0x03 EBTR1 Table Read Protection Block 1 Block 1 (001000-001FFFh) protected from table reads executed in other blocks Block 1 (001000-001FFFh) not protected from table reads executed in other blocks EBTR0 Table Read Protection Block 0 Block 0 (000200-000FFFh) protected from table reads executed in other blocks Block 0 (000200-000FFFh) not protected from table reads executed in other blocks CONFIG7H · 0x30000D 0x40 default 0x40 EBTRB Boot Block Table Read Protection bit Boot Block (000000-0001FFh) protected from table reads executed in other blocks Boot Block (000000-0001FFh) not protected from table reads executed in other blocks 
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