PIC18LF6493 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1H · 0x300001 0x07 default 0x07 IESO Internal External Switch Over Mode Oscillator Switchover mode disabled Oscillator Switchover mode enabled FCMEN Fail-Safe Clock Monitor Enable Fail-Safe Clock Monitor disabled Fail-Safe Clock Monitor enabled OSC Oscillator LP oscillator XT oscillator HS oscillator External RC oscillator, CLKO function on RA6 EC oscillator, CLKO function on RA6 EC oscillator, port function on RA6 HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) External RC oscillator, port function on RA6 Internal oscillator block, port function on RA6 and RA7 Internal oscillator block, CLKO function on RA6, port function on RA7 CONFIG2L · 0x300002 0x1F default 0x1F BORV Brown Out Voltage VBOR set to 4.6V VBOR set to 4.3V VBOR set to 2.8V VBOR set to 2.1V BOREN Brown Out Detect Brown-out Reset disabled in hardware and software Brown-out Reset enabled and controlled by software (SBOREN is enabled) Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) Brown-out Reset enabled in hardware only (SBOREN is disabled) PWRT Power Up Timer PWRT enabled PWRT disabled CONFIG2H · 0x300003 0x1F default 0x1F WDTPS Watchdog Postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 WDT Watchdog Timer WDT disabled (control is placed on the SWDTEN bit) WDT enabled CONFIG3L · 0x300004 0xFF default 0xFF RES RESERVED RESERVED RESERVED CONFIG3H · 0x300005 0x81 default 0x81 MCLRE Master Clear Enable RG5 input pin enabled; MCLR disabled MCLR pin enabled; RG5 input pin disabled LPT1OSC Low Power Timer1 Osc enable Timer1 configured for higher power operation Timer1 configured for low-power operation CCP2MX CCP2 Mux CCP2 input/output is multiplexed with RE7 CCP2 input/output is multiplexed with RC1 CONFIG4L · 0x300006 0x81 default 0x81 DEBUG Background Debugger Enable bit Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins XINST Extended Instruction Set Enable bit Instruction set extension and Indexed Addressing mode disabled (Legacy mode) Instruction set extension and Indexed Addressing mode enabled STVREN Stack Overflow Reset Stack full/underflow will not cause Reset Stack full/underflow will cause Reset CONFIG5L · 0x300008 0x01 default 0x01 CP Code Protect 00000-03FFF Program memory block (000000-003FFFh) code-protected Program memory block (000000-003FFFh) not code-protected CONFIG7L · 0x30000C 0xFF default 0xFF RES RESERVED 1 · unprogrammed 0 · programmed 
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