PIC24EP256GU814 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FGS · 0xF80004 0xFFFFCF default 0xFFFFCF GSSK General Segment Key bits General Segment Write Protection and Code Protection is Disabled General Segment Write Protection or Code Protection is Enabled GSS General Segment Code-Protect bit Standard Security Code protection Enabled General Segment Code protect is disabled GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written FOSCSEL · 0xF80006 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source FNOSC Initial Oscillator Source Selection bits Internal Fast RC (FRC) Internal Fast RC with PLL (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator (XT, HS, EC) with PLL Secondary Oscillator (SOSC) Low-Power RC Oscillator (LPRC) Internal Fast RC (FRC) Oscillator with divide-by-16 Internal Fast RC (FRC) Oscillator with postscaler FOSC · 0xF80008 0xFFFFFF default 0xFFFFFF FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral pin select configuration Allow multiple reconfigurations Allow only one reconfiguration OSCIOFNC OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select bits EC (External Clock) Mode XT Crystal Oscillator Mode HS Crystal Oscillator Mode Primary Oscillator disabled FWDT · 0xF8000A 0xFFFFFF default 0xFFFFFF FWDTEN Watchdog Timer Enable bit Watchdog timer enabled/disabled by user software Watchdog timer always enabled WINDIS Watchdog Timer Window Enable bit Watchdog Timer in Window mode Watchdog Timer in Non-Window mode PLLKEN PLL Lock Wait Enable bit Clock switch will not wait for the PLL lock signal. Clock switch to PLL source will wait until the PLL lock signal is valid. WDTPRE Watchdog Timer Prescaler bit 1:32 1:128 WDTPOST Watchdog Timer Postscaler bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xF8000C 0xFFFFFF default 0xFFFFFF ALTI2C2 Alternate I2C pins for I2C2 ASDA2/ASCK2 pins are selected as the I/O pins for I2C2 SDA2/SCK2 pins are selected as the I/O pins for I2C2 ALTI2C1 Alternate I2C pins for I2C1 ASDA1/ASCK1 pins are selected as the I/O pins for I2C1 SDA1/SCK1 pins are selected as the I/O pins for I2C1 BOREN Brown-out Reset (BOR) Detection Enable bit BOR is disabled BOR is enabled FPWRT Power-on Reset Timer Value Select bits Disabled 2ms 4ms 8ms 16ms 32ms 64ms 128ms FICD · 0xF8000E 0xFFFFDF default 0xFFFFDF JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ATMOD8 Entry into Alt TMOD8 is enabled Entry into Alt TMOD8 is disabled RSTPRI Reset Target Vector Select bit Device will obtain reset instruction from Aux flash Device will obtain reset instruction from Primary flash ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGEC3 and PGED3 Communicate on PGEC2 and PGED2 Communicate on PGEC1 and PGED1 FAS · 0xF80010 0xFFFFCF default 0xFFFFCF APLK Auxiliary Segment Key bits Aux Flash Write Protection and Code Protection is Disabled Aux Flash Write Protection or Code Protection is Enabled APL Auxiliary Segment Code-protect bit Aux Flash Code protect is enabled Aux Flash Code protect is disabled AWRP Auxiliary Segment Write-protect bit Aux Flash is write protected Aux Flash may be written 
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