PIC24F08KA101 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FBS · 0xF80000 0x000F default 0x000F BSS Boot segment Protect High security boot program Flash segment starts at 200h, ends at 000AFEh Standard security, boot program Flash segment starts at 200h, ends at 000AFEh No boot program Flash segment BWRP Table Write Protect Boot Boot segment is write-protected Boot segment may be written FGS · 0xF80004 0x0003 default 0x0003 GCP General Segment Code Flash Code Protection bit Standard security enabled No protection GWRP General Segment Code Flash Write Protection bit General segment is write-protected General segment may be written FOSCSEL · 0xF80006 0x0087 default 0x0087 IESO Internal External Switch Over bit Internal External Switchover mode disabled (Two-Speed Start-up disabled) Internal External Switchover mode enabled (Two-Speed Start-up enabled) FNOSC Oscillator Select Fast RC oscillator (FRC) Fast RC oscillator with divide-by-N with PLL module (FRCDIV+PLL) Primary oscillator (XT, HS, EC) Primary oscillator with PLL module (HS+PLL, EC+PLL) Secondary oscillator (SOSC) Low-Power RC oscillator (LPRC) 500 kHz Low-Power FRC oscillator with divide-by-N (LPFRCDIV) 8 MHz FRC oscillator with divide-by-N (FRCDIV) FOSC · 0xF80008 0x00FF default 0x00FF FCKSM Clock Switching and Monitor Selection Both Clock Switching and Fail-safe Clock Monitor are enabled Clock switching is enabled, Fail-Safe Clock Monitor is disabled Both Clock Switching and Fail-safe Clock Monitor are disabled 3 (not named) SOSCSEL SOSC Power Selection Configuration bits Secondary oscillator configured for low-power operation Secondary oscillator configured for high-power operation POSCFREQ Primary Oscillator Frequency Range Configuration bits Primary oscillator/external clock input frequency less than 100 kHz Primary oscillator/external clock input frequency between 100 kHz and 8 MHz Primary oscillator/external clock input frequency greater than 8 MHz OSCIOFNC CLKO Enable Configuration bit CLKO output disabled; pin functions as port I/O CLKO output signal is active on the OSCO pin POSCMOD Primary Oscillator Configuration bits External clock mode selected XT oscillator mode selected HS oscillator mode selected Primary oscillator disabled FWDT · 0xF8000A 0x00DF default 0x00DF FWDTEN Watchdog Timer Enable bit WDT disabled (control is placed on the SWDTEN bit) WDT enabled WINDIS Windowed Watchdog Timer Disable bit Windowed WDT enabled Standard WDT selected; windowed WDT disabled FWPSA WDT Prescaler WDT prescaler ratio of 1:32 WDT prescaler ratio of 1:128 WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xF8000C 0x00FB default 0x00FB MCLRE MCLR Pin Enable bit RA5 input pin enabled; MCLR disabled MCLR pin enabled; RA5 input pin disabled BORV Brown-out Reset Voltage bits Low-power Brown-Out Reset occurs around 2.0V Brown-out Reset set to Highest Voltage (2.7V) Brown-out Reset set at 2.0V Brown-out Reset set to lowest voltage (1.8V) I2C1SEL Alternate I2C1 Pin Mapping bit Alternate location for SCL1/SDA1 pins Default location for SCL1/SDA1 pins PWRTEN Power-up Timer Enable bit PWRT disabled PWRT enabled BOREN Brown-out Reset Enable bits Brown-out Reset disabled in hardware; SBOREN bit disabled Brown-out Reset controlled with the SBOREN bit setting Brown-out Reset enabled only while device is active and disabled in Sleep; SBOREN bit disabled Brown-out Reset enabled in hardware; SBOREN bit disabled FICD · 0xF8000E 0x00C3 default 0x00C3 BKBUG Background Debugger Enable bit Background debugger functions enabled Background debugger disabled ICS ICD Pin Placement Select bits PGC3/PGD3 are used for programming and debugging the device PGC2/PGD2 are used for programming and debugging the device PGC1/PGD1 are used for programming and debugging the device FDS · 0xF80010 0x00FF default 0x00FF DSWDTEN Deep Sleep Watchdog Timer Enable bit DSWDT disabled DSWDT enabled DSBOREN Deep Sleep Zero-Power BOR Enable bit Deep Sleep BOR disabled in Deep Sleep Deep Sleep BOR enabled in Deep Sleep RTCOSC RTCC Reference Clock Select bit RTCC uses LPRC as reference clock RTCC uses SOSC as reference clock DSWDTOSC DSWDT Reference Clock Select bit DSWDT uses SOSC as reference clock DSWDT uses LPRC as reference clock DSWDTPS Deep Sleep Watchdog Timer Postscale Select bits 1:2 (2.1 ms) 1:8 (8.3 ms) 1:32 (33 ms) 1:128 (132 ms) 1:512 (528 ms) 1:2048 (2.1 Seconds) 1:8192 (8.5 Seconds) 1:32,768 (34 Seconds) 1:131,072 (135 Seconds) 1:524,288 (9 Minutes) 1:2,097,152 (36 Minutes) 1:8,388,608 (2.4 Hours) 1:33,554,432 (9.6 Hours) 1:134,217,728 (38.5 Hours) 1:536,870,912 (6.4 Days) 1:2,147,483,648 (25.7 Days) 
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