PIC24F08KL201 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FBS · 0xF80000 0xFFFF default 0xFFFF BSS Boot segment Protect High Security Boot Protect 000200 - 000AFE Standard Security Boot Protect 000200 - 000AFE No boot flash segment BWRP Boot Segment Write Protect Enabled Disabled FGS · 0xF80004 0xFFFF default 0xFFFF GCP General Segment Code Protect Standard security enabled No Protection GWRP General Segment Flash Write Protect General segment is write-protected General segment may be written FOSCSEL · 0xF80006 0xFFF9 default 0xFFF9 IESO Internal External Switch Over bit Internal External Switchover mode disabled (Two-speed Start-up disabled) Internal External Switchover mode enabled (Two-speed Start-up enabled) LPRCSEL LPRC Power and Accuracy Low Power/Low Accuracy High Power/High Accuracy SOSCSRC SOSC Source Type Digital Mode for use with external clock on SCLKI Analog Mode for use with crystal FNOSC Oscillator Select Fast RC Oscillator (FRC) Fast RC Oscillator with Postscaler and PLL (FRCDIV+PLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL (XT+PLL, HS+PLL, EC+PLL) Secondary Oscillator (SOSC) Low Power RC Oscillator (LPRC) 500KHz Low Power FRC with Postscaler (LPFRC) 8MHz FRC with Postscaler (FRCDIV) FOSC · 0xF80008 0xFF3B default 0xFF3B FCKSM Clock Switching and Monitor Selection Clock Switching and Fail-safe Clock Monitor Enabled Clock Switching Enabled; Fail-safe Clock Monitor Disabled Clock Switching and Fail-safe Clock Monitor Disabled SOSCSEL SOSC Power Selection Configuration bits Secondary Oscillator configured for low-power operation Secondary Oscillator configured for high-power operation POSCFREQ Primary Oscillator Frequency Range Primary Oscillator/External Clock frequency <100kHz Primary Oscillator/External Clock frequency between 100kHz to 8MHz Primary Oscillator/External Clock frequency >8MHz OSCIOFNC CLKO Pin I/O Function Port I/O enabled (CLKO disabled) CLKO output signal enabled POSCMD Primary Oscillator Mode External clock mode selected XT oscillator mode selected HS oscillator mode selected Primary oscillator disabled FWDT · 0xF8000A 0xFFDF default 0xFFDF FWTEN0 Watchdog Timer Enable bits WDT disabled in hardware; SWDTEN bit disabled WDT enabled while device is active; SWDTEN bit disabled WDT controlled with SWDTEN bit setting WDT enabled in hardware WINDIS Windowed Watchdog Timer Disable bit Windowed WDT enabled Standard WDT selected (windowed WDT disabled) FWPSA WDT Prescaler bit WDT prescaler ratio of 1:32 WDT prescaler ratio of 1:128 WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 FPOR · 0xF8000C 0xFFFF default 0xFFFF MCLRE MCLR Pin Enable bit RA5 input enabled; MCLR disabled RA5 input disabled; MCLR enabled BORV Brown-out Reset Voltage bits Low-power Brown-Out Reset occurs around 2.0V Brown-out Reset at 3.0V Brown-out Reset at 2.7V Brown-out Reset at 1.8V I2C1SEL Alternate I2C1 Pin Mapping bit Alternate ASCL1/ASDA1 Pins for I2C1 Default SCL1/SDA1 Pins for I2C1 PWRTEN Power-up Timer Enable PWRT disabled PWRT enabled BOREN Brown-out Reset Enable bits Brown-out Reset disabled in hardware; SBOREN bit disabled Brown-out Rest controlled by SBOREN bit Enabled only while device is active; SBOREN bit disabled Enabled in hardware; SBOREN bit disabled FICD · 0xF8000E 0xFFFF default 0xFFFF DEBUG Background Debugger Enable bit Background debugger functions enabled Background debugger disabled ICS ICD Pin Placement Select EMUC/EMUD share PGC3/PGD3 EMUC/EMUD share PGC2/PGD2 EMUC/EMUD share PGC1/PGD1 
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