PIC24F08KM102 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FBS · 0xF80000 0xFFFF default 0xFFFF BSS Boot segment Protect High Security Boot Protect 000200h - 000AFEh Standard Security Boot Protect 000200h - 000AFEh No boot program flash segment BWRP Boot Segment Write Protect Enabled Disabled FGS · 0xF80004 0xFFFF default 0xFFFF GCP General Segment Code Protect Standard security enabled No Protection GWRP General Segment Write Protect General segment is write-protected General segment may be written FOSCSEL · 0xF80006 0xFFFF default 0xFFFF IESO Internal External Switch Over bit Internal External Switchover mode disabled (Two-speed Start-up disabled) Internal External Switchover mode enabled (Two-speed Start-up enabled) LPRCSEL LPRC Oscillator Power and Accuracy Low Power, Low Accuracy Mode High Power, High Accuracy Mode SOSCSRC SOSC Source Type Digital Mode for use with external source Analog Mode for use with crystal FNOSC Oscillator Select Fast RC Oscillator (FRC) Fast RC Oscillator with Postscaler and PLL Module (FRCDIV+PLL) Primary Oscillator (XT, HS, EC) Primary oscillator with PLL Module (HS+PLL, EC+PLL) Secondary oscillator (SOSC) Low Power RC oscillator (LPRC) 500kHz Low-Power FRC oscillator with Postscaler(LPFRCDIV) 8MHz FRC oscillator With Postscaler (FRCDIV) FOSC · 0xF80008 0xFFFF default 0xFFFF FCKSM Clock Switching and Monitor Selection Both Clock Switching and Fail-safe Clock Monitor are enabled Clock Switching is enabled, Fail-safe Clock Monitor is disabled Both Clock Switching and Fail-safe Clock Monitor are disabled 3 (not named) SOSCSEL SOSC Power Selection Configuration bits Secondary Oscillator configured for low-power operation Secondary Oscillator configured for high-power operation POSCFREQ Primary Oscillator Frequency Range Configuration bits Primary oscillator/external clock input frequency less than 100kHz Primary oscillator/external clock input frequency between 100kHz and 8MHz Primary oscillator/external clock input frequency greater than 8MHz OSCIOFNC CLKO Enable Configuration bit Port I/O enabled (CLKO disabled) CLKO output signal enabled POSCMOD Primary Oscillator Configuration bits External clock mode selected XT oscillator mode selected HS oscillator mode selected Primary oscillator disabled FWDT · 0xF8000A 0xFFFF default 0xFFFF FWTEN0 Watchdog Timer Enable bits WDT disabled in hardware; SWDTEN bit disabled WDT enabled while device is active and disabled in Sleep; SWDTEN bit disabled WDT controlled with the SWDTEN bit setting WDT enabled in hardware WINDIS Windowed Watchdog Timer Disable bit Windowed WDT enabled Standard WDT selected(windowed WDT disabled) FWPSA WDT Prescaler bit WDT prescaler ratio of 1:32 WDT prescaler ratio of 1:128 WDTPS Watchdog Timer Postscale Select bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 FPOR · 0xF8000C 0xFFFF default 0xFFFF MCLRE MCLR Pin Enable bit RA5 input pin enabled, MCLR disabled RA5 input pin disabled, MCLR pin enabled BORV Brown-out Reset Voltage bits Low-power Brown-Out Reset occurs around 2.0V Brown-out Reset set to Highest Voltage (3.0V) Brown-out Reset set at 2.7V Brown-out Reset set to lowest voltage (1.8V) I2C1SEL Alternate I2C1 Pin Mapping bit Use Alternate ASCL1/ASDA1 Pins For I2C1 Use Default SCL1/SDA1 Pins For I2C1 PWRTEN Power-up Timer Enable bit PWRT disabled PWRT enabled BOREN Brown-out Reset Enable bits Brown-out Reset disabled in hardware, SBOREN bit disabled Brown-out Rest controlled by SBOREN bit Brown-out Reset enabled only while device is active and disabled in SLEEP, SBOREN bit disabled Brown-out Reset enabled in hardware, SBOREN bit disabled FICD · 0xF8000E 0xFFFF default 0xFFFF BKBUG Background Debugger Enable bit Background debugger functions enabled Background debugger disabled ICS ICD Pin Placement Select bits EMUC/EMUD share PGC3/PGD3 EMUC/EMUD share PGC2/PGD2 EMUC/EMUD share PGC1/PGD1 
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