PIC24FJ128GB412 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x015780), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0x15780 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table Disable bit Enable AIVT Disable AIVT CSS Configuration Segment Code Protection Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Program Write Protection bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code Protect High Security Standard Security Code protection is disabled GWRP General Segment Write Protect General segment is write-protected Writes to program memory are allowed BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot segment Protect High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write Protect Boot segment is write-protected Boot segment may be written FBSLIM · 0x15790 0xFFFFFF default 0xFFFFFF BSLIM Boot Segment Code Flash Page Address Limit bits FSIGN · 0x15794 0xFF7FFF default 0xFF7FFF Reserved Reserved 1 · unprogrammed 0 · programmed FOSCSEL · 0x15798 0xFFFFFF default 0xFFFFFF IESO Internal External Switchover Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source PLLMODE Frequency Multiplier Select Bits 96 MHz PLL (4 MHz input) 96 MHz PLL (8 MHz input) 96 MHz PLL (12 MHz input) 96 MHz PLL (16 MHz input) 96 MHz PLL (20 MHz input) 96 MHz PLL (24 MHz input) 96 MHz PLL (32 MHz input) 96 MHz PLL (48 MHz input) 4x PLL selected 6x PLL selected 8x PLL selected No PLL used; PLLEN bit is not available FNOSC Oscillator Select Fast RC Oscillator (FRC) Fast RC Oscillator with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) Secondary Oscillator (SOSC) Low-Power RC Oscillator (LPRC) Fast RC Oscillator with divide-by-n (FRCDIV) FOSC · 0x1579C 0xFFFFFF default 0xFFFFFF FCKSM Clock Switching and Monitor Selection Clock switching is enabled, Fail-Safe Clock Monitor is enabled Clock switching is enabled, Fail-Safe Clock Monitor is disabled Clock switching and Fail-Safe Clock Monitor are disabled 3 (not named) IOL1WAY IOLOCK One-Way Set Enable The IOLOCK bit can be set and cleared using the unlock sequence Once set the IOLOCK bit cannot be cleared PLLSS PLL Secondary Selection Configuration bit PLL is fed by the on-chip Fast RC (FRC) oscillator PLL is fed by the Primary oscillator SOSCSEL SOSC Power Selection Configuration bits Digital (SCLKI) mode SOSC is used in crystal (SOSCI/SOSCO) mode OSCIOFCN OSCO Pin Configuration OSCO/CLKO/RC15 functions as port I/O (RC15) OSCO/CLKO/RC15 functions as CLKO (FOSC/2) POSCMOD Primary Oscillator Select External clock mode selected XT oscillator mode selected HS Oscillator mode selected Primary Oscillator disabled FWDT · 0x157A0 0xFFFFFF default 0xFFFFFF WDTCLK WDT Clock Source Select bits WDT uses system clock when active, LPRC while in Sleep mode WDT uses SOSC input WDT uses 31 kHz source from FRC when active in Windowed WDT WDT uses LPRC WDTCMX WDT Clock Source Select bits WDT always uses LPRC as its clock source WDT clock source is determined by the WDTCLK Configuration bits WDTWIN Watchdog Window Select bits Watch Dog Timer Window Width is 75 percent Watch Dog Timer Window Width is 50 percent Watch Dog Timer Window Width is 37.5 percent Watch Dog Timer Window Width is 25 percent WINDIS Windowed Watchdog Timer Disable bit Windowed WDT enabled Standard Watchdog Timer enabled (Windowed-mode is disabled) FWDTEN Watchdog Timer Enable Watchdog Timer is disabled WDT enabled only while device active and disabled in Sleep WDT controlled with the SWDTEN bit Watchdog Timer is enabled FWPSA WDT Prescaler Prescaler ratio of 1:32 Prescaler ratio of 1:128 WDTPS Watchdog Timer Postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0x157A4 0xFFFF7F default 0xFFFF7F LPCFG Low power regulator control Enabled Disabled BOREN Brown-out Reset Enable bits Brown-out Reset Disabled Brown-out Reset Enable FICD · 0x157A8 0xFFFFDF default 0xFFFFDF BTSWP BOOTSWP Instruction Enable bit BOOTSWP instruction is enabled BOOTSWP instruction is disabled DEBUG Background Debug Device resets into Debug mode Device resets into Operational mode JTAGEN JTAG Port Enable JTAG port is disabled JTAG port is enabled ICS Emulator Pin Placement Select bits Emulator functions are shared with PGEC3/PGED3 Emulator functions are shared with PGEC2/PGED2 Emulator functions are shared with PGEC1/PGED1 FDS · 0x157AC 0xFFFFFF default 0xFFFFFF DSSWEN Deep Sleep Software Control Select Bit Deep Sleep disabled Deep Sleep enabled and controlled by the DSEN bit DSWDTEN Deep Sleep Watchdog Timer Enable bit DSWDT disabled DSWDT enabled DSBOREN Deep Sleep Zero-Power BOR Enable bit Deep Sleep BOR disabled in Deep Sleep Deep Sleep BOR enabled in Deep Sleep DSWDTOSC DSWDT Reference Clock Select bit DSWDT uses Secondary Oscillator (SOSC) DSWDT uses Low Power RC Oscillator (LPRC) DSWDTPS Deep Sleep Watchdog Timer Postscale Select bits 1:32 (1 ms) 1:64 (2.1 ms) 1:128 (4.1 ms) 1:256 (8.3 ms) 1:512 (16.5 ms) 1:1,024 (33 ms) 1:2,048 (66.1 ms) 1:4,096 (132.1 ms) 1:8,192 (264.3 ms) 1:16,384 (528.5 ms) 1:32,768 (1.057s) 1:65,536 (2.114s) 1:131,072 (4.228s) 1:262,114 (8.456s) 1:524,288 (16.912s) 1:1,048,576 (33.825s) 1:2,097,152 (67.7s) 1:4,194,304 (135.3s) 1:8,388,608 (4.5 minutes) 1:16,777,216 (9.0 minutes) 1:33,554,432 (18.0 minutes) 1:67,108,864 (36.1 minutes) 1:134,217,728 (72.2 minutes) 1:268,435,456 (2.4 hours) 1:536,870,912 (4.8 hours) 1:1,073,741,824 (9.6 hours) 1:2,147,483,648 (19.2 hours) 1:4,294,967,296 (38.5 hours) 1:8,589,934592 (77.0 hours) 1:17,179,869,184 (6.4 days) 1:34,359,738,368(12.8 days) 1:68,719,476,736 (25.7 days) FDEVOPT1 · 0x157B0 0xFFFFFF default 0xFFFFFF ALTVREF Alternate VREF location Enable VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1) VREF is on a default pin (VREF+ on RA10 and VREF- on RA9) TMPRWIPE RAM Based Entryption Key Wipe Enable bit Cryptographic Engine Key RAM is erased when a TMPR pin event is detected Cryptographic Engine Key RAM is not erased onTMPR pin events TMPRPIN Tamper Pin Enable bit TMPRN pin function is enabled TMPRN pin function is disabled ALTCMPI Alternate Comparator Input Enable bit C1INC, C2INC and C3INC are on RG9 C1INC, C2INC, and C3INC are on their standard pin locations FBTSEQ · 0x157FC 0xFFFFFF default 0xFFFFFF IBSEQ The one's complement of BSEQ; must be calculated by the user and written during device programming. BSEQ Relative value defining which partition will be active after devie Reset; the partition containing a lower boot number will be active. 
BETA