PIC24FJ256GA606 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x02AF00), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0x2AF00 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table bit Enabled AIVT Disabled AIVT CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0x2AF10 0x001FFF default 0x001FFF BSLIM Boot Segment Flash Page Address Limit bits FSIGN · 0x2AF14 0xFF7FFF default 0xFF7FFF SIGN Signature Bit FOSCSEL · 0x2AF18 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source PLLMODE PLL Mode Selection 96 MHz PLL. (4 MHz input) 96 MHz PLL. (8 MHz input) 96 MHz PLL. (12 MHz input) 96 MHz PLL. (16 MHz input) 96 MHz PLL. (20 MHz input) 96 MHz PLL. (24 MHz input) 96 MHz PLL. (32 MHz input) 96 MHz PLL. (48 MHz input) 4x PLL selected 6x PLL selected 8x PLL selected No PLL used; PLLEN bit is not available FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Secondary Oscillator (SOSC) Low-Power RC Oscillator (LPRC) Digitally-Controlled Oscillator Oscillator with Frequency Divider FOSC · 0x2AF1C 0xFFFFFF default 0xFFFFFF FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral pin select configuration bit Allow multiple reconfigurations Allow only one reconfiguration PLLSS PLL Secondary Selection Configuration bit PLL is fed by the on-chip Fast RC (FRC) oscillator PLL is fed by the Primary oscillator SOSCSEL SOSC Power Selection Configuration bits Digital (SCLKI) mode SOSC is used in crystal (SOSCI/SOSCO) mode OSCIOFCN OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select bits EC (External Clock) Mode XT Crystal Oscillator Mode HS Crystal Oscillator Mode Primary Oscillator disabled FWDT · 0x2AF20 0xFFFFFF default 0xFFFFFF WDTCLK WDT Clock Source Select bits WDT uses system clock when active, LPRC while in Sleep mode WDT uses SOSC inpu WDT uses 31 kHz source from FRC when active in Windowed WDT WDT uses LPRC WDTCMX WDT MUX Source Select bits WDT always uses LPRC as its clock source WDT clock source is determined by the WDTCLK Configuration bits WDTWIN Watchdog Timer Window Select bits WDT Windo is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period WINDIS Watchdog Timer Window Enable bit Watchdog Timer in Window mode Watchdog Timer in Non-Window mode FWDTEN Watchdog Timer Enable bits WDT and SWDTEN disabled WDT Enabled only while device is active (disabled in sleep, SWDTEN disabled) WDT Enabled/Disabled (controlled using SWDTEN bit) WDT Enabled FWPSA Watchdog Timer Prescaler bit 1:32 1:128 WDTPS Watchdog Timer Postscaler bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0x2AF24 0xFFFFFF default 0xFFFFFF DNVPEN Downside Voltage Protection Enable bit Downside protection disabled when BOR is inactive Downside protection enabled using ZPBOR when BOR is inactive LPCFG Low power regulator control Retention Sleep controlled by RETEN No Retention Sleep BOREN Brown Out Enable bit Brown Out Disabled Controlled by SBOREN Disabled for Sleep Modes Brown Out Enable Bit FICD · 0x2AF28 0xFFFFDF default 0xFFFFDF BTSWP BOOTSWP Disable BOOTSWP instruction is enabled BOOTSWP instruction disabled BACKBUG Debug Enabled Enabled Disabled JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGEC3 and PGED3 Communicate on PGEC2 and PGED2 Communicate on PGEC1 and PGED1 FDEVOPT1 · 0x2AF2C 0xFFFFFF default 0xFFFFFF ALTVREF Alternate Voltage Reference Location Enable bit VREF+ and CVREF+ on RB0, VREF- and CVREF- on RB1 VREF+ and CVREF+ on RA10, VREF- and CVREF- on RA9 SOSCHP SOSC High Power Enable bit (valid only when SOSCSEL = 1 Enable SOSC low power mode Enable SOSC high power mode (default) TMPRPIN Tamper Pin Enable bit TMPRN pin function is enabled TMPRN pin function is disabled ALTCMPI Alternate Comparator Input Enable bit C1INC, C2INC and C3INC are on RG9 C1INC, C2INC, and C3INC are on their standard pin locations 
BETA