PIC24FJ256GL405 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x02AF00), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0x2AF00 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table bit Enabled AIVT Disabled AIVT CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0x2AF10 0xFFFFFF default 0xFFFFFF BSLIM Boot Segment Flash Page Address Limit bits FSIGN · 0x2AF14 0xFF7FFF default 0xFF7FFF SIGN Signature Bit FOSCSEL · 0x2AF18 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source PLLMODE PLL Mode Selection 96 MHz PLL. Oscillator input is divided by 1 (4 MHz input) 96 MHz PLL. Oscillator input is divided by 2 (8 MHz input) 96 MHz PLL. Oscillator input is divided by 3 (12 MHz input) 96 MHz PLL. Oscillator input is divided by 4 (16 MHz input) 96 MHz PLL. Oscillator input is divided by 5 (20 MHz input) 96 MHz PLL. Oscillator input is divided by 6 (24 MHz input) 96 MHz PLL. Oscillator input is divided by 8 (32 MHz input) 96 MHz PLL. Oscillator input is divided by 12 (48 MHz input) 4x PLL selected 6x PLL selected 8x PLL selected No PLL used; PLLEN bit is not available FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Secondary Oscillator (SOSC) Low-Power RC Oscillator (LPRC) Oscillator with Divider FOSC · 0x2AF1C 0xFFFFFF default 0xFFFFFF FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled and Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral pin select configuration bit Allow multiple reconfigurations Allow only one reconfiguration PLLSS PLL Secondary Selection Configuration bit PLL is fed by the on-chip Fast RC (FRC) oscillator PLL is fed by the Primary oscillator SOSCEN SOSC Power Selection Configuration bits SOSC crystal driver is disabled (RC13/RC14 mode) SOSC crystal driver is enabled (SOSCI/SOSCO mode) OSCIOFCN OSC2 Pin Function bit RC15 is general purpose digital I/O pin RC15 (CLKO) outputs CPU clock POSCMD Primary Oscillator Mode Select bits EC (External Clock) mode XT Crystal Oscillator mode HS Crystal Oscillator mode Primary Oscillator disabled FWDT · 0x2AF20 0xFFFFFF default 0xFFFFFF WDTCLK WDT Clock Source Select bits WDT uses system clock when active, LPRC while in Sleep mode WDT uses SOSC input WDT uses 32 kHz source from FRC when active in windowed mode WDT uses LPRC WDTCMX WDT MUX Source Select bits WDT always uses LPRC as its clock source WDT clock source is determined by the WDTCLK Configuration bits WDTWIN Watchdog Timer Window Select bits WDT window is 75% of WDT period WDT window is 50% of WDT period WDT window is 37.5% of WDT period WDT window is 25% of WDT period WINDIS Watchdog Timer Window Enable bit WDT in windowed mode WDT in non-windowed mode FWDTEN Watchdog Timer Enable bits WDT and SWDTEN are disabled WDT is enabled only while device is active (disabled in sleep, SWDTEN disabled) WDT and SWDTEN are enabled (can be controlled by SWDTEN bit) WDT is always enabled (cannot be controlled by SWDTEN) FWPSA Watchdog Timer Prescaler bit 1:32 1:128 WDTPS Watchdog Timer Postscaler bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0x2AF24 0xFFFFFF default 0xFFFFFF LPBOREN Downside Voltage Protection Enable bit Low power BOR is disabled when BOR is inactive Low power BOR is enabled when BOR is inactive LPREGEN Low power regulator control Low power regulator controlled by RETEN is enabled Low power regulator is disabled BOREN Brown Out Enable bit Brown Out is disabled Controlled by SBOREN Disabled in Sleep Modes Brown Out is enabled FICD · 0x2AF28 0xFFFFDF default 0xFFFFDF BTSWP BOOTSWP Instruction Enable bit BOOTSWP instruction is enabled BOOTSWP instruction is disabled BKBUG Debug Enable bit Enabled Disabled JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGEC3 and PGED3 Communicate on PGEC2 and PGED2 Communicate on PGEC1 and PGED1 FDMTIVTL · 0x2AF2C 0xFFFFFF default 0xFFFFFF DMTIVTL DMT Window Interval Lower 16 bits FDMTIVTH · 0x2AF30 0xFFFFFF default 0xFFFFFF DMTIVTH DMT Window Interval Upper 16 bits FDMTCNTL · 0x2AF34 0xFFFFFF default 0xFFFFFF DMTCNTL DMT Instruction Count Time-out Value Lower 16 bits FDMTCNTH · 0x2AF38 0xFFFFFF default 0xFFFFFF DMTCNTH DMT Instruction Count Time-out Value Higher 16 bits FDMT · 0x2AF3C 0xFFFFFF default 0xFFFFFF DMTDIS DMT Disable bit Dead Man Timer is enabled and cannot be disabled by software Dead Man Timer is disabled and can be enabled by software FDEVOPT1 · 0x2AF40 0xFFFFFF default 0xFFFFFF SMB3EN SMBus 3 Enable bit Normal SMBus input levels SMBus 3.0 input levels ALTI2C1 Alternate I2C pin Location ASDA1 and ASCL1 on RB5 and RB4 SDA1 and SCL1 on RA15 and RA14 SOSCHP SOSC High Power Enable bit (valid only when SOSCSEL = 1 SOSC low power mode SOSC high power mode (default) TMPRPIN Tamper Pin Enable bit TMPRN pin function is enabled TMPRN pin function is disabled ALTCMPI Alternate Comparator Input Enable bit AC2INC and AC3INC are on RG7 C2INC and C3INC are on RG9 and RD11 
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